summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAndrew Waterman2016-08-07 17:11:24 -0700
committerAndrew Waterman2016-08-09 13:05:13 -0700
commit2a074c828ddd8e6c20fa21d618664d50120f3d7a (patch)
tree0b5486b62293d90d4b17ff18dc36044fff3740be /src
parentc907eabfb65cd6442e35588b095ca031e2bdad7a (diff)
Support Module name overrides with "override def desiredName"
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala30
1 files changed, 16 insertions, 14 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 08646cf9..31856541 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -46,18 +46,21 @@ private class Emitter(circuit: Circuit) {
}
// Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
- private val defnMap = collection.mutable.HashMap[String, String]()
+ private val defnMap = collection.mutable.HashMap[(String, String), Component]()
// Map of Component name to FIRRTL id.
private val moduleMap = collection.mutable.HashMap[String, String]()
- /** Generates the FIRRTL module definition with a specified name.
+ /** Generates the FIRRTL module declaration.
*/
- private def moduleDefn(m: Component, name: String): String = {
+ private def moduleDecl(m: Component): String = m.id match {
+ case _: BlackBox => newline + s"extmodule ${m.name} : "
+ case _: Module => newline + s"module ${m.name} : "
+ }
+
+ /** Generates the FIRRTL module definition.
+ */
+ private def moduleDefn(m: Component): String = {
val body = new StringBuilder
- m.id match {
- case _: BlackBox => body ++= newline + s"extmodule $name : "
- case _: Module => body ++= newline + s"module $name : "
- }
withIndent {
for (p <- m.ports)
body ++= newline + emitPort(p)
@@ -82,21 +85,20 @@ private class Emitter(circuit: Circuit) {
*/
private def emit(m: Component): String = {
// Generate the body.
- val moduleName = m.id.getClass.getName.split('.').last
- val defn = moduleDefn(m, moduleName)
+ val defn = moduleDefn(m)
- defnMap get defn match {
- case Some(deduplicatedName) =>
- moduleMap(m.name) = deduplicatedName
+ defnMap get (m.id.desiredName, defn) match {
+ case Some(duplicate) =>
+ moduleMap(m.name) = duplicate.name
""
case None =>
require(!(moduleMap contains m.name),
"emitting module with same name but different contents")
moduleMap(m.name) = m.name
- defnMap(defn) = m.name
+ defnMap((m.id.desiredName, defn)) = m
- moduleDefn(m, m.name)
+ moduleDecl(m) + defn
}
}