diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 7 | ||||
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 30 |
2 files changed, 21 insertions, 16 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index ca91c5f8..5af744c4 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -57,8 +57,11 @@ extends HasId { private[core] val _ids = ArrayBuffer[HasId]() dynamicContext.currentModule = Some(this) - /** Name of the instance. */ - val name = Builder.globalNamespace.name(getClass.getName.split('.').last) + /** Desired name of this module. */ + def desiredName = this.getClass.getName.split('.').last + + /** Legalized name of this module. */ + final val name = Builder.globalNamespace.name(desiredName) /** IO for this Module. At the Scala level (pre-FIRRTL transformations), * connections in and out of a Module may only go through `io` elements. diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 08646cf9..31856541 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -46,18 +46,21 @@ private class Emitter(circuit: Circuit) { } // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. - private val defnMap = collection.mutable.HashMap[String, String]() + private val defnMap = collection.mutable.HashMap[(String, String), Component]() // Map of Component name to FIRRTL id. private val moduleMap = collection.mutable.HashMap[String, String]() - /** Generates the FIRRTL module definition with a specified name. + /** Generates the FIRRTL module declaration. */ - private def moduleDefn(m: Component, name: String): String = { + private def moduleDecl(m: Component): String = m.id match { + case _: BlackBox => newline + s"extmodule ${m.name} : " + case _: Module => newline + s"module ${m.name} : " + } + + /** Generates the FIRRTL module definition. + */ + private def moduleDefn(m: Component): String = { val body = new StringBuilder - m.id match { - case _: BlackBox => body ++= newline + s"extmodule $name : " - case _: Module => body ++= newline + s"module $name : " - } withIndent { for (p <- m.ports) body ++= newline + emitPort(p) @@ -82,21 +85,20 @@ private class Emitter(circuit: Circuit) { */ private def emit(m: Component): String = { // Generate the body. - val moduleName = m.id.getClass.getName.split('.').last - val defn = moduleDefn(m, moduleName) + val defn = moduleDefn(m) - defnMap get defn match { - case Some(deduplicatedName) => - moduleMap(m.name) = deduplicatedName + defnMap get (m.id.desiredName, defn) match { + case Some(duplicate) => + moduleMap(m.name) = duplicate.name "" case None => require(!(moduleMap contains m.name), "emitting module with same name but different contents") moduleMap(m.name) = m.name - defnMap(defn) = m.name + defnMap((m.id.desiredName, defn)) = m - moduleDefn(m, m.name) + moduleDecl(m) + defn } } |