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2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
* still trying to find right mix * Making some progress on Mux1H * Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general Catches some additional problem edge cases Some tests that illustrate most of this * Moved in Angie's code for handling FixedPoint case Cleaned up tests considerably, per @ducky64 review * Just a bit more cleanup
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
Fixes #554
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
Using the sample_element of the created wire is incorrect because Wires have no direction so the Wire constructed for a Vec of Module IO was constructed incorrectly. Fixes #569 and resolves #522.
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
Make it relatively easy to override a single CompileOption.
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
Fixes #567
2017-03-28Creating FixedPoint literals was throwing away width when specifically provided.chick
This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
This also allows asUInt/asTypeOf to work properly on those Bundles, even though zero-width wire support is lacking.
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
Use fold(0) instead of reduce to handle the corner case.
2017-03-24Fixed fix, allow Mux of different binary points and widths (#559)Richard Lin
Allow muxing FxP of different widths and BPs
2017-03-17Add single arg constructor back to compatibility reg (#553)Richard Lin
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)" This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2. This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality. * Add missing implicits to Vec.apply() signature. * Use correct macro (CompileOptionsTransform) for indexWhere.
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Move log2Up and log2Down to compatibility wrapperAndrew Waterman
2017-03-08Avoid log2Up in testsAndrew Waterman
2017-03-08Avoid log2Up in ShiftRegisterTesterAndrew Waterman
This is an odd one. Using log2Ceil directly results in a Verilator compile error, presumably due to a FIRRTL zero-width wire bug.
2017-03-08Improve UIntToOH behavior on incorrect inputs; avoid log2UpAndrew Waterman
The old implementation failed to check for width <= -2, and did the wrong thing when -1 was explicitly passed. Splitting into two methods avoids the latter issue. log2Ceil's argument might be 1, so employ a max operator.
2017-03-08In OHToUInt, use log2Ceil instead of log2UpAndrew Waterman
Since the argument is at least 2, this change has no semantic effect.
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
Since the argument is at least 2, this change has no semantic effect.
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
Both should be zero-width wires.
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
Provide a better error message when length < 0. Change log2Up in log2Ceil, which has no effect, since the argument is always at least 2.
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
It always should throw an exception when n < 0, but in the specific case of x.isWidthKnown && x.getWidth == 1, it failed to do so. This commit also changes log2Up in log2Ceil, which has no effect, since the argument is always at least 2.
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
* Use test_run_dir for more tests. * Use official option and DRY. Make "test_run_dir" the default for ChiselSpec. Verify output files are created in DriverSpec tests.
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
Fixes #501. Also added UIntOps test.
2017-02-24Test that large Vecs can have widths inferredjackkoenig
Test for ucb-bar/firrtl#407
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
* Bugfix #513. Needs better test case * Improved test
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
* Fix up Absolute value #abs Defines #abs in Num Implement #abs in UInt Change #abs in SInt to return an SInt Change #abs in FixedPoint to return a FixedPoint Added a couple of tests Add some scala style suppression to Bits so I can read code in IntelliJ * Per review Add tests that abs works for positive values Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec Used fixed point literals in fixed points abs definition
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
* Added vec IO tests for #104 * Added Vec test case for Reg of vecs * Change Vec creation to check if gen is lit (and hence needs to be declared) Fixes #104 * Fix tests (add IO())), Vec.fill() * Fix deprecated usage. * Add Binding IO() NPE fix so tests pass. * Fix style - use space consistently. * Fix style - use space consistently.
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
* Move to cookbook * Change FSM implementation to use switch & is * Add non-FSM implementation * Add execution-driven test
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-31Make Module and Bundle properly use empty namespacesJack
Fix default suggested name of Module instances (now based on desired name rather than actual assigned name). Remove parent/child relationship from Namespace. Previously, Module and Bundle namespaces were "children" of the Module definition namespace. This could lead to collisions that would give unexpected names for module instances or Bundle elements. In particular, otherwise identical modules that instantiate other identical modules in such a way that the instance cannot be named via reflection would not be deduplicated because the names of the instances would collide with the names of the modules in the Builder.globalNamespace.
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
2017-01-30Add shift register with reset (#439)Stevo
* [stevo]: add reset initialization to shift register * [stevo]: better comment * [stevo]: add tests, fix bug
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
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