summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into big-decimal-methods-for-num-typesChick Markley
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
* Change when thunks return type to Any Changes the type of the thunk for when and WhenContext methods from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) where a when thunk is returning something other than Unit that is then discarded, e.g., another WhenContext. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change switch thunk return to type to Any Changes the type of switch thunks from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) when the internals of a switch block return something other than Unit which is then discarded. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Removed unnecessary castChick Markley
Non-functional, must have been a typo
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2020-01-21specifying type of target field (#1305)Deborah Soung
2020-01-17Bugfix: Select.instances now works with blackboxes (#1303)Adam Izraelevitz
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2019-12-18Add method asBool to Clock.chick
Shortcut for .asUInt.asBool Added test to show it works
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big ↵chick
decimal - made .F and .I work for creating fixed point and interval lits from big decimal - Added NumObject trait which provides new math conversions - Made a Num object that extends NumObject - Add this trait to FixedPoint and Interval for backward compatibility - Removed code that is now in NumObject, keeping things DRY - Add tests to FixedPointSpec to show lit conversion to double and big decimal - Add tests to IntervalSpec to show lit conversion to double and big decimal - Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
2019-12-18BitPat supports whitespace and underscores, presumably for human readability.chick
The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-16Remove unused WriteEmitted phase (#1273)Schuyler Eldridge
This removes a dead line where a WriteEmitted phase is constructed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11- add simple test of IntervalRange helperschick
- getLowestPossibleValue - getHighestPossibleValue - getPossibleValues
2019-12-06Revert "Compat compile options macro (#1253)" (#1268)Jack Koenig
This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Compat compile options macro (#1253)Jack Koenig
* Use macro to materialize CompileOptions in Chisel._ This switches from using an implicit val that required awkward suppression (as illustrated in CompileOptionsSpec) to allowing overriding in the same way as done in "import chisel3._" via the creation of an implicit val in lexical scope. * Deprecate Chisel.defaultCompileOptions
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-05Add tests for exhaustive MuxLookup optimizationAlbert Magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Don't use MuxLookup default for full mappingSchuyler Eldridge
This modifies MuxLookup to not use the 'default' mapping argument if a "full" mapping is provided. A "full" mapping enumerates all possible cases for a 'key' argument of a known size. This will check literal values to ensure exhaustiveness holds. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-02Tests for anonymous/class-in-module desiredNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-23Make ChiselStage targets not privateColin Schmidt
This enables users to use the nice run method of `ChiselStage` with their own set of phases.
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
This fixes a bug where internal boring using BoringUtils.bore would fail because it was using instanceName which cannot be called before the module closes. Previously, this meant that BoringUtils.bore would work for boring instances (which are closed in a parent), but not for boring signals in the current, unclosed module. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-13Add requirements to Queue class (#1176)Jack Koenig
FIRRTL barfs on negative and zero-sized memories
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-27Test stack trace trimming for ChiselStageSchuyler Eldridge
Use FIRRTL stage-style testing to check stdout printing without and with --full-stacktrace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Enable --module command line argumentSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Move stack trimming from Driver to ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add test that stack trace trimming worksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Remove stack trace trimming in Elaborate phaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add firrtlTests.Utils methodsSchuyler Eldridge
This adds methods for examining stdout/stderr and exit codes inside of a Scala program. This are pulled directly from firrtlTests, but we aren't currently publishing those anywhere that we can get at them. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
Migrate Driver to use a PhaseManager to internally resolve Phase ordering. This requires the use of an identity node to adequately describe the necessary prerequisite/dependents. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Migrate ChiselStage to use the DependencyAPISchuyler Eldridge
Modifies ChiselStage to use a PhaseManager for Phase ordering. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-28 08:46:17 +0000