Add read-under-write parameter to SyncReadMem (#1183)

* Add support for readUnderWrite to SyncReadMem

* Add write collision behavior test to MemorySpec

* Update constant names

2 files changed, 29 insertions, 1 deletions

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 3409ce94..1341b5f6 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -69,7 +69,7 @@ private class Emitter(circuit: Circuit) {
       case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
       case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
-      case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}]"
+      case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit
       case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index ebdb1483..49085f9b 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -33,6 +33,30 @@ class SyncReadMemTester extends BasicTester {
   }
 }
 
+class SyncReadMemWriteCollisionTester extends BasicTester {
+  val (cnt, _) = Counter(true.B, 5)
+
+  // Write-first
+  val m0 = SyncReadMem(2, UInt(2.W), SyncReadMem.WriteFirst)
+  val rd0 = m0.read(cnt)
+  m0.write(cnt, cnt)
+
+  // Read-first
+  val m1 = SyncReadMem(2, UInt(2.W), SyncReadMem.ReadFirst)
+  val rd1 = m1.read(cnt)
+  m1.write(cnt, cnt)
+
+  // Read data from address 0
+  when (cnt === 3.U) {
+    assert(rd0 === 2.U)
+    assert(rd1 === 0.U)
+  }
+
+  when (cnt === 4.U) {
+    stop()
+  }
+}
+
 class SyncReadMemWithZeroWidthTester extends BasicTester {
   val (cnt, _) = Counter(true.B, 3)
   val mem      = SyncReadMem(2, UInt(0.W))
@@ -81,6 +105,10 @@ class MemorySpec extends ChiselPropSpec {
     assertTesterPasses { new SyncReadMemTester }
   }
 
+  property("SyncReadMem write collision behaviors should work") {
+    assertTesterPasses { new SyncReadMemWriteCollisionTester }
+  }
+
   property("SyncReadMem should work with zero width entry") {
     assertTesterPasses { new SyncReadMemWithZeroWidthTester }
   }