diff options
| author | Chick Markley | 2020-02-03 09:38:44 -0800 |
|---|---|---|
| committer | GitHub | 2020-02-03 09:38:44 -0800 |
| commit | 4f1f638663a7176ac28d95d71c14a37021314c3b (patch) | |
| tree | b1377a66921f953458523b54b531298f56beeb69 /src | |
| parent | f1c4395bd608234fef5a60d8851036d1acb2382f (diff) | |
| parent | efc40252631869531e79f4d8490113d18e75cc1d (diff) | |
Merge pull request #1285 from freechipsproject/add-asbool-to-clock
Add method asBool to Clock.
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/Clock.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 58a491ef..5dea66dc 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -7,6 +7,7 @@ import chisel3.testers.BasicTester class ClockAsUIntTester extends BasicTester { assert(true.B.asClock.asUInt === 1.U) + assert(true.B.asClock.asBool === true.B) stop() } @@ -18,6 +19,7 @@ class WithClockAndNoReset extends RawModule { val a = withClock(clock2) { RegNext(in) } + out := a } |
