Merge pull request #1285 from freechipsproject/add-asbool-to-clock

Add method asBool to Clock.

2 files changed, 8 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Clock.scala b/chiselFrontend/src/main/scala/chisel3/Clock.scala
index 87674e7b..d7975b1e 100644
--- a/chiselFrontend/src/main/scala/chisel3/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Clock.scala
@@ -2,7 +2,8 @@
 
 package chisel3
 
-import chisel3.internal.Builder.{pushOp}
+import scala.language.experimental.macros
+import chisel3.internal.Builder.pushOp
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo._
 import chisel3.internal.firrtl.PrimOp.AsUIntOp
@@ -30,6 +31,10 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
   /** Not really supported */
   def toPrintable: Printable = PString("CLOCK")
 
+  /** Returns the contents of the clock wire as a [[Bool]]. */
+  final def asBool(): Bool = macro SourceInfoTransform.noArg
+  def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt().asBool()
+
   override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
   private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
index 58a491ef..5dea66dc 100644
--- a/src/test/scala/chiselTests/Clock.scala
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -7,6 +7,7 @@ import chisel3.testers.BasicTester
 
 class ClockAsUIntTester extends BasicTester {
   assert(true.B.asClock.asUInt === 1.U)
+  assert(true.B.asClock.asBool === true.B)
   stop()
 }
 
@@ -18,6 +19,7 @@ class WithClockAndNoReset extends RawModule {
   val a = withClock(clock2) {
     RegNext(in)
   }
+
   out := a
 }