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-rw-r--r--src/test/scala/chiselTests/Clock.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
index 58a491ef..5dea66dc 100644
--- a/src/test/scala/chiselTests/Clock.scala
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -7,6 +7,7 @@ import chisel3.testers.BasicTester
class ClockAsUIntTester extends BasicTester {
assert(true.B.asClock.asUInt === 1.U)
+ assert(true.B.asClock.asBool === true.B)
stop()
}
@@ -18,6 +19,7 @@ class WithClockAndNoReset extends RawModule {
val a = withClock(clock2) {
RegNext(in)
}
+
out := a
}