Merge branch 'master' into big-decimal-methods-for-num-types

# Conflicts:
#	src/test/scala/chiselTests/IntervalSpec.scala

6 files changed, 40 insertions, 10 deletions

diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 612cdcc7..390f82a5 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -80,8 +80,11 @@ object Select {
     */
   def instances(module: BaseModule): Seq[BaseModule] = {
     check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case i: DefInstance => i.id
+    module._component.get match {
+      case d: DefModule => d.commands.collect {
+        case i: DefInstance => i.id
+      }
+      case other => Nil
     }
   }
 
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 0a0cc47c..df23f97d 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -16,7 +16,7 @@ import java.io.{StringWriter, PrintWriter}
 class ChiselStage extends Stage with PreservesAll[Phase] {
   val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli
 
-  val targets =
+  val targets: Seq[PhaseManager.PhaseDependency] =
     Seq( classOf[chisel3.stage.phases.Checks],
          classOf[chisel3.stage.phases.Elaborate],
          classOf[chisel3.stage.phases.AddImplicitOutputFile],
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 83475d1b..7c0abdb2 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -14,7 +14,7 @@ object BitPat {
     * @return bits the literal value, with don't cares being 0
     * @return mask the mask bits, with don't cares being 0 and cares being 1
     * @return width the number of bits in the literal, including values and
-    * don't cares.
+    * don't cares, but not including the white space and underscores
     */
   private def parse(x: String): (BigInt, BigInt, Int) = {
     // Notes:
@@ -25,14 +25,17 @@ object BitPat {
     require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'")
     var bits = BigInt(0)
     var mask = BigInt(0)
+    var count = 0
     for (d <- x.tail) {
-      if (d != '_') {
+      if (! (d == '_' || d.isWhitespace)) {
         require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d)
         mask = (mask << 1) + (if (d == '?') 0 else 1)
         bits = (bits << 1) + (if (d == '1') 1 else 0)
+        count += 1
       }
     }
-    (bits, mask, x.length - 1)
+
+    (bits, mask, count)
   }
 
   /** Creates a [[BitPat]] literal from a string.
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 59ad6324..44cacccc 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -36,8 +36,18 @@ class DecoderSpec extends ChiselPropSpec {
   val bitpatPair = for(seed <- Arbitrary.arbitrary[Int]) yield {
     val rnd = new scala.util.Random(seed)
     val bs = seed.toBinaryString
-    val bp = bs.map(if(rnd.nextBoolean) _ else "?").mkString
-    ("b" + bs, "b" + bp)
+    val bp = bs.map(if(rnd.nextBoolean) _ else "?")
+
+    // The following randomly throws in white space and underscores which are legal and ignored.
+    val bpp = bp.map { a =>
+      if (rnd.nextBoolean) {
+        a
+      } else {
+        a + (if (rnd.nextBoolean) "_" else " ")
+      }
+    }.mkString
+
+    ("b" + bs, "b" + bpp)
   }
   private def nPairs(n: Int) = Gen.containerOfN[List, (String,String)](n,bitpatPair)
 
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala
index ae7fdabf..ee704c83 100644
--- a/src/test/scala/chiselTests/IntervalSpec.scala
+++ b/src/test/scala/chiselTests/IntervalSpec.scala
@@ -456,7 +456,7 @@ class IntervalSpec extends FreeSpec with Matchers with ChiselRunners {
           () =>
             new BasicTester {
               val x = 5.I(range"[0,4]")
-            }
+          }
         ).elaborate
       }
     }
diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala
index f3c756ab..80ab518f 100644
--- a/src/test/scala/chiselTests/aop/SelectSpec.scala
+++ b/src/test/scala/chiselTests/aop/SelectSpec.scala
@@ -7,7 +7,9 @@ import chiselTests.ChiselFlatSpec
 import chisel3._
 import chisel3.aop.Select.{PredicatedConnect, When, WhenNot}
 import chisel3.aop.{Aspect, Select}
-import firrtl.{AnnotationSeq}
+import chisel3.experimental.ExtModule
+import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation}
+import firrtl.AnnotationSeq
 
 import scala.reflect.runtime.universe.TypeTag
 
@@ -139,5 +141,17 @@ class SelectSpec extends ChiselFlatSpec {
     )
   }
 
+  "Blackboxes" should "be supported in Select.instances" in {
+    class BB extends ExtModule { }
+    class Top extends RawModule {
+      val bb = Module(new BB)
+    }
+    val top = ChiselGeneratorAnnotation(() => {
+      new Top()
+    }).elaborate(1).asInstanceOf[DesignAnnotation[Top]].design
+    val bbs = Select.collectDeep(top) { case b: BB => b }
+    assert(bbs.size == 1)
+  }
+
 }