diff options
| author | Schuyler Eldridge | 2019-12-16 15:07:55 -0500 |
|---|---|---|
| committer | mergify[bot] | 2019-12-16 20:07:55 +0000 |
| commit | 4ef91c4c43d6ab808e79edd239062f919a5bbbe3 (patch) | |
| tree | ed8776dfcb2cf055733eba2525ad547d231f95ca /src | |
| parent | 954cc41e1349d0df6d2250d6270590340cd36e82 (diff) | |
Remove unused WriteEmitted phase (#1273)
This removes a dead line where a WriteEmitted phase is constructed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/stage/package.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala index 67d38ae7..57766be6 100644 --- a/src/main/scala/chisel3/stage/package.scala +++ b/src/main/scala/chisel3/stage/package.scala @@ -28,7 +28,6 @@ package object stage { private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] { - lazy val dummyWriteEmitted = new firrtl.stage.phases.WriteEmitted lazy val dummyConvert = new Convert lazy val dummyEmitter = new Emitter |