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authorJack Koenig2019-09-13 10:05:57 -0700
committerGitHub2019-09-13 10:05:57 -0700
commit14503966b017d160e46cc7e401c2ffa2c39212e8 (patch)
treed9c16ac797765a090059f3781fb991422f2c2c92 /src
parent3d65ccee36fd97c26d170f631322ad0c2c9d6dd7 (diff)
Fix Queue.apply for size 0 in chisel3._ code (#1177)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala2
-rw-r--r--src/test/scala/chiselTests/CompatibilitySpec.scala1
-rw-r--r--src/test/scala/chiselTests/QueueSpec.scala40
3 files changed, 41 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 15b4ab1d..841f90e6 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -277,7 +277,7 @@ object Queue
pipe: Boolean = false,
flow: Boolean = false): DecoupledIO[T] = {
if (entries == 0) {
- val deq = Wire(new DecoupledIO(enq.bits))
+ val deq = Wire(new DecoupledIO(chiselTypeOf(enq.bits)))
deq.valid := enq.valid
deq.bits := enq.bits
enq.ready := deq.ready
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index c602efa3..d2b39c49 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
val dcd = Wire(Decoupled(data))
dcd shouldBe a [DecoupledIO[UInt]]
Queue(dcd) shouldBe a [DecoupledIO[UInt]]
+ Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]]
Enum(UInt(), 2) shouldBe a [List[UInt]]
ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]]
Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt]
diff --git a/src/test/scala/chiselTests/QueueSpec.scala b/src/test/scala/chiselTests/QueueSpec.scala
index c26e9485..0f798e09 100644
--- a/src/test/scala/chiselTests/QueueSpec.scala
+++ b/src/test/scala/chiselTests/QueueSpec.scala
@@ -25,7 +25,7 @@ class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int
inCnt.inc()
}
when(q.io.deq.fire()) {
- //ensure that what comes otu is what comes in
+ //ensure that what comes out is what comes in
assert(elems(outCnt.value) === q.io.deq.bits)
outCnt.inc()
}
@@ -169,6 +169,33 @@ class QueueFlowTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I
}
}
+class QueueFactoryTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: Int) extends BasicTester {
+ val enq = Wire(Decoupled(UInt(bitWidth.W)))
+ val deq = Queue(enq, queueDepth)
+
+ val elems = VecInit(elements.map {
+ _.asUInt()
+ })
+ val inCnt = Counter(elements.length + 1)
+ val outCnt = Counter(elements.length + 1)
+
+ enq.valid := (inCnt.value < elements.length.U)
+ deq.ready := LFSR(16)(tap)
+
+ enq.bits := elems(inCnt.value)
+ when(enq.fire()) {
+ inCnt.inc()
+ }
+ when(deq.fire()) {
+ //ensure that what comes out is what comes in
+ assert(elems(outCnt.value) === deq.bits)
+ outCnt.inc()
+ }
+ when(outCnt.value === elements.length.U) {
+ stop()
+ }
+}
+
class QueueSpec extends ChiselPropSpec {
// Disable shrinking on error.
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -233,4 +260,15 @@ class QueueSpec extends ChiselPropSpec {
}
}
}
+
+ property("Queue companion object factory method should work") {
+ forAll(vecSizes, safeUIntN(20), Gen.choose(0, 15)) { (depth, se, tap) =>
+ whenever(se._1 >= 1 && se._2.nonEmpty) {
+ assertTesterPasses {
+ new QueueFactoryTester(se._2, depth, se._1, tap)
+ }
+ }
+ }
+
+ }
}