diff options
| author | Schuyler Eldridge | 2020-02-06 12:17:14 -0500 |
|---|---|---|
| committer | GitHub | 2020-02-06 12:17:14 -0500 |
| commit | a505d23ecfbeae91c8b3ba306c5ce186d3f08c29 (patch) | |
| tree | 20c8c011718aaff7a2068108e4af23e60ad2838c /src | |
| parent | b171f20d945487c79b18c18a2e8db98254f6e3e9 (diff) | |
| parent | 6a3eb3188c983268fab0f64ef4681b403cc2052d (diff) | |
Merge pull request #1315 from freechipsproject/emit-orr-andr
Emit FIRRTL andr, orr for Bits.{andR, orR}
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/BitwiseOps.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 505178a4..20e3f01a 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -13,6 +13,8 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { assert((a & b) === (_a & _b).asUInt) assert((a | b) === (_a | _b).asUInt) assert((a ^ b) === (_a ^ _b).asUInt) + assert((a.orR) === (_a != 0).asBool) + assert((a.andR) === (s"%${w}s".format(BigInt(_a).toString(2)).foldLeft(true)(_ && _ == '1') ).asBool) stop() } |