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Chisel with SFC compatibility
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Reg.scala
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Author
2022-01-10
Apply scalafmt
Jack Koenig
2021-05-09
Fix ShiftRegister with 0 delay. (#1903)
Jiuyang Liu
2021-05-06
add ShiftRegisters to expose register inside ShiftRegister. (#1723)
Jiuyang Liu
2020-10-01
Move Chisel3 to SPDX license conventions (#1604)
Chick Markley
2020-06-22
Use ChiselStage in Tests
Schuyler Eldridge
2019-05-20
Repackagecore rebase (#1078)
Jim Lawson
2017-03-08
Deprecate old Reg with nulls constructor (#455)
Richard Lin
2017-01-30
Add shift register with reset (#439)
Stevo
2016-11-21
Restyle a lot of test code, mainly with regex
ducky
2016-10-14
Implement a standardized execution scheme for chisel
chick
2016-09-29
Massive rename of CompileOptions.
Jim Lawson
2016-09-01
Move connection implicits from Module constructor to connection methods.
Jim Lawson
2016-08-16
Merge branch 'master' into sdtwigg_connectwrap_renamechisel3
Jim Lawson
2016-08-15
Make "def width" a private API; expose isWidthKnown instead (#257)
Andrew Waterman
2016-07-25
Minimize differences with master.
Jim Lawson
2016-07-20
More literal/width rangling.
Jim Lawson
2016-07-20
Distinguish between ?Int.Lit and ?Int.width
Jim Lawson
2016-07-19
Incorporate connection logic.
Jim Lawson
2016-07-18
Update Chisel -> chisel3 references.
Jim Lawson
2016-06-20
Rename "package", "import", and explicit references to "chisel3".
Jim Lawson
2016-06-08
Rename Chisel -> chisel in tests
ducky
2015-12-06
Split internal and FIRRTL packages
ducky
2015-11-04
Use elaborate for elaboration tests, not execute
Henry Cook
2015-10-23
Add Scalaland unit tests for Reg
ducky