Restyle a lot of test code, mainly with regex

1 files changed, 5 insertions, 5 deletions

diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 90992c01..43e64fe7 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -17,7 +17,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      val reg = Reg(t=UInt(2.W), next=Wire(UInt(3.W)), init=20.U)
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
@@ -25,13 +25,13 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20))
+      val reg1 = Reg(next=Wire(UInt(3.W)), init=20.U)
       reg1.isWidthKnown should be (false)
       DataMirror.widthOf(reg1).known should be (false)
-      val reg2 = Reg(init=UInt(20))
+      val reg2 = Reg(init=20.U)
       reg2.isWidthKnown should be (false)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5))
+      val reg3 = Reg(next=Wire(UInt(3.W)), init=5.U)
       reg3.isWidthKnown should be (false)
       DataMirror.widthOf(reg3).known should be (false)
     }
@@ -40,7 +40,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
-      val reg2 = Reg(init=UInt(20, width=7))
+      val reg2 = Reg(init=20.U(7.W))
       reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }