Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 16 insertions, 15 deletions

diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index a02e6fa5..c814a030 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -13,19 +13,19 @@ class RegSpec extends ChiselFlatSpec {
   "Reg" should "be of the same type and width as t" in {
     class RegOutTypeWidthTester extends BasicTester {
       val reg = Reg(UInt(2.W))
-      DataMirror.widthOf(reg) should be (2.W)
+      DataMirror.widthOf(reg) should be(2.W)
     }
-    ChiselStage.elaborate{ new RegOutTypeWidthTester }
+    ChiselStage.elaborate { new RegOutTypeWidthTester }
   }
 
   "RegNext" should "be of unknown width" in {
     class RegUnknownWidthTester extends BasicTester {
       val reg1 = RegNext(2.U(3.W))
-      DataMirror.widthOf(reg1).known should be (false)
+      DataMirror.widthOf(reg1).known should be(false)
       val reg2 = RegNext(2.U(3.W), 4.U)
-      DataMirror.widthOf(reg2).known should be (false)
+      DataMirror.widthOf(reg2).known should be(false)
       val reg3 = RegNext(2.U(3.W), 4.U(5.W))
-      DataMirror.widthOf(reg3).known should be (false)
+      DataMirror.widthOf(reg3).known should be(false)
     }
     ChiselStage.elaborate { new RegUnknownWidthTester }
   }
@@ -33,11 +33,11 @@ class RegSpec extends ChiselFlatSpec {
   "RegInit" should "have width only if specified in the literal" in {
     class RegForcedWidthTester extends BasicTester {
       val reg1 = RegInit(20.U)
-      DataMirror.widthOf(reg1).known should be (false)
+      DataMirror.widthOf(reg1).known should be(false)
       val reg2 = RegInit(20.U(7.W))
-      DataMirror.widthOf(reg2) should be (7.W)
+      DataMirror.widthOf(reg2) should be(7.W)
     }
-    ChiselStage.elaborate{ new RegForcedWidthTester }
+    ChiselStage.elaborate { new RegForcedWidthTester }
   }
 }
 
@@ -52,22 +52,22 @@ class ShiftTester(n: Int) extends BasicTester {
 }
 
 class ShiftResetTester(n: Int) extends BasicTester {
-  val (cntVal, done) = Counter(true.B, n-1)
+  val (cntVal, done) = Counter(true.B, n - 1)
   val start = 23.U
   val sr = ShiftRegister(cntVal + 23.U, n, 1.U, true.B)
   when(done) {
-    assert(sr === (if(n == 0) cntVal + 23.U else 1.U))
+    assert(sr === (if (n == 0) cntVal + 23.U else 1.U))
     stop()
   }
 }
 
 class ShiftRegisterSpec extends ChiselPropSpec {
   property("ShiftRegister should shift") {
-    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses{ new ShiftTester(shift) } }
+    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses { new ShiftTester(shift) } }
   }
 
   property("ShiftRegister should reset all values inside") {
-    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses{ new ShiftResetTester(shift) } }
+    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses { new ShiftResetTester(shift) } }
   }
 }
 
@@ -76,8 +76,9 @@ class ShiftsTester(n: Int) extends BasicTester {
   val start = 23.U
   val srs = ShiftRegisters(cntVal + start, n)
   when(RegNext(done)) {
-    srs.zipWithIndex.foreach{ case (data, index) =>
-      assert(data === (23 + n - 1 - index).U)
+    srs.zipWithIndex.foreach {
+      case (data, index) =>
+        assert(data === (23 + n - 1 - index).U)
     }
     stop()
   }
@@ -85,6 +86,6 @@ class ShiftsTester(n: Int) extends BasicTester {
 
 class ShiftRegistersSpec extends ChiselPropSpec {
   property("ShiftRegisters should shift") {
-    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses{ new ShiftsTester(shift) } }
+    forAll(Gen.choose(0, 4)) { (shift: Int) => assertTesterPasses { new ShiftsTester(shift) } }
   }
 }