Add Scalaland unit tests for Reg

1 files changed, 43 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
new file mode 100644
index 00000000..77d10d98
--- /dev/null
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -0,0 +1,43 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import Chisel._
+import Chisel.testers.BasicTester
+
+class RegSpec extends ChiselFlatSpec {
+  "A Reg" should "throw an exception if not given any parameters" in {
+    a [ChiselException] should be thrownBy {
+      val reg = Reg()
+    }
+  }
+
+  "A Reg" should "be of the same type and width as outType, if specified" in {
+    class RegOutTypeWidthTester extends BasicTester {
+      val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
+      reg.width.get should be (2)
+    }
+    assert(execute{new RegOutTypeWidthTester})
+  }
+
+  "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
+    class RegUnknownWidthTester extends BasicTester {
+      val reg1 = Reg(next=UInt(width=3), init=UInt(20))
+      reg1.width.known should be (false)
+      val reg2 = Reg(init=UInt(20))
+      reg2.width.known should be (false)
+      val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
+      reg3.width.known should be (false)
+    }
+    assert(execute{new RegUnknownWidthTester})
+  }
+
+  "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
+    class RegForcedWidthTester extends BasicTester {
+      val reg2 = Reg(init=UInt(20, width=7))
+      reg2.width.get should be (7)
+    }
+    assert(execute{new RegForcedWidthTester})
+  }
+}