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path: root/src/test/scala/chiselTests/MultiClockSpec.scala
AgeCommit message (Collapse)Author
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-06-01Literals set their ref so they no longer get named (#826)Jack Koenig
Fixes #763 Add tests for #763 and #472 This has a few implications * Constructing a literal no longer increments _T_ suffixes * Internally, wrapping a literal Bits in Node(...) will work * Literal Bools work in withReset/withClockAndReset
2017-08-17More of the bindings refactor (#635)Richard Lin
Rest of the binding refactor
2017-08-17Make Reset a trait (#672)Jack Koenig
Bool implements Reset. Compatibility package includes an implicit conversion from Reset to Bool.
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
Fixes #567
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.