summaryrefslogtreecommitdiff
path: root/src/main
AgeCommit message (Expand)Author
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-19Add support for Input() and Output() (available in Chisel2 since ucb-bar/chis...Jim Lawson
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Style fixesducky
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04work on new style literal accessorsducky
2018-07-02Direct to FIRRTL (#829)Jack Koenig
2018-06-25Correcting documentation errors in Arbiter.scala (#839)Brendan Sweeney
2018-06-20Programmatic Port Creation (#833)Jack Koenig
2018-06-18Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)Wesley W. Terpstra
2018-05-24Fix UIntToOH for output widths larger than 2^(input width) (#823)Andrew Waterman
2018-02-28Refactor Annotations (#767)Jack Koenig
2018-02-21Support zero-entry queues (but not for irrevocable) (#780)Andrew Waterman
2018-02-07Cloning IO with compatibility 🦆 (#754)Richard Lin
2018-02-02Autoclonetype will clone args that are of type data (#768)Richard Lin
2018-01-23Runtime API deprecation warnings (#761)Richard Lin
2018-01-02Support for inner classes, implicit parameter lists, supertypessducky64
2018-01-02Autoclonetype initial prototypeducky
2017-12-19Add WireInit.apply that accepts DontCare (#731)Jack Koenig
2017-12-14Fix a few compiler warnings (#738)Jack Koenig
2017-12-13Improve some of the ScalaDoc in chisel3.utilJack Koenig
2017-11-23Change switch to emit when, elsewhen, instead of when, when (#720)Jack Koenig
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
2017-10-26Invalidateapi (#645)Adam Izraelevitz
2017-10-05the cloneType and chiselCloneType hot mess 🔥 (#653)Richard Lin
2017-10-03Remove warning in Queue for compatibility code (#702)Jack Koenig
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-17More of the bindings refactor (#635)Richard Lin
2017-08-17Make Reset a trait (#672)Jack Koenig
2017-08-15Make .dir give correct direction for Module io in compatibilityJack Koenig
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-08-01Address scalastyle issues, out of date comments, extraneous imports. (#658)Jim Lawson
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-07-07Ensure IO is non-null before attempting to autoWrapPorts. (#643)Jim Lawson
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-05-31Add dontTouch for annotating Data to not be removedJack Koenig
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
2017-05-28Correct misleading example codeEdward Wang
2017-05-25Update internal Pipe wiring - fixes #615" (#616)Jim Lawson
2017-05-19Update comments describing Decoupled/ReadyValid - fix #437. (#493)Jim Lawson
2017-05-11Scope resources - move them down into chisel3 directory - fixes #549 (#610)Jim Lawson
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 10:20:19 +0000