summaryrefslogtreecommitdiff
path: root/src/main
diff options
context:
space:
mode:
authorAndrew Waterman2018-02-21 18:07:17 -0800
committerGitHub2018-02-21 18:07:17 -0800
commit98177d3647e51efe869de1031872adb6406fa34d (patch)
treee4fa94bfe4a833b6fcc4e7e748760270f8ffe4a3 /src/main
parent5c75a40cff58f14fcb71490ddcd2db5a466a5105 (diff)
Support zero-entry queues (but not for irrevocable) (#780)
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala20
1 files changed, 15 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index d2419325..f9fc2b90 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -282,11 +282,20 @@ object Queue
entries: Int = 2,
pipe: Boolean = false,
flow: Boolean = false): DecoupledIO[T] = {
- val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow))
- q.io.enq.valid := enq.valid // not using <> so that override is allowed
- q.io.enq.bits := enq.bits
- enq.ready := q.io.enq.ready
- TransitName(q.io.deq, q)
+ if (entries == 0) {
+ val deq = Wire(new DecoupledIO(enq.bits))
+ deq.valid := enq.valid
+ deq.bits := enq.bits
+ enq.ready := deq.ready
+ deq
+ } else {
+ require(entries > 0)
+ val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow))
+ q.io.enq.valid := enq.valid // not using <> so that override is allowed
+ q.io.enq.bits := enq.bits
+ enq.ready := q.io.enq.ready
+ TransitName(q.io.deq, q)
+ }
}
/** Create a queue and supply a IrrevocableIO containing the product.
@@ -300,6 +309,7 @@ object Queue
entries: Int = 2,
pipe: Boolean = false,
flow: Boolean = false): IrrevocableIO[T] = {
+ require(entries > 0) // Zero-entry queues don't guarantee Irrevocability
val deq = apply(enq, entries, pipe, flow)
val irr = Wire(new IrrevocableIO(deq.bits))
irr.bits := deq.bits