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authorRichard Lin2017-08-11 13:05:44 -0700
committerGitHub2017-08-11 13:05:44 -0700
commitc87145bc61a729bb035428d527c5787c174c5256 (patch)
tree99f9dbe4f3fca852a4e890619d5dace0cb3677dd /src/main
parent43e62e7f6b5534b48c3757cfcca51b66ca74753d (diff)
Rename userDir->specifiedDir (#671)
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala10
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala26
2 files changed, 18 insertions, 18 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 8fa995e4..33e8e75c 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -29,7 +29,7 @@ package object Chisel { // scalastyle:ignore package.object.name
}
implicit class AddDirMethodToData[T<:Data](val target: T) extends AnyVal {
- import chisel3.core.{DataMirror, ActualDirection, UserDirection}
+ import chisel3.core.{DataMirror, ActualDirection, SpecifiedDirection}
def dir: Direction = {
DataMirror.isSynthesizable(target) match {
case true => target match {
@@ -41,10 +41,10 @@ package object Chisel { // scalastyle:ignore package.object.name
}
case _ => NODIR
}
- case false => DataMirror.userDirectionOf(target) match { // returns local direction only
- case UserDirection.Unspecified => NODIR
- case UserDirection.Input => INPUT
- case UserDirection.Output => OUTPUT
+ case false => DataMirror.specifiedDirectionOf(target) match { // returns local direction only
+ case SpecifiedDirection.Unspecified => NODIR
+ case SpecifiedDirection.Input => INPUT
+ case SpecifiedDirection.Output => OUTPUT
case dir => throw new RuntimeException(s"Unexpected element direction '$dir'")
}
}
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index c7a7f6a4..963a713b 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -2,7 +2,7 @@
package chisel3.internal.firrtl
import chisel3._
-import chisel3.core.UserDirection
+import chisel3.core.SpecifiedDirection
import chisel3.experimental._
import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
@@ -13,15 +13,15 @@ private[chisel3] object Emitter {
private class Emitter(circuit: Circuit) {
override def toString: String = res.toString
- private def emitPort(e: Port, topDir: UserDirection=UserDirection.Unspecified): String = {
- val resolvedDir = UserDirection.fromParent(topDir, e.dir)
+ private def emitPort(e: Port, topDir: SpecifiedDirection=SpecifiedDirection.Unspecified): String = {
+ val resolvedDir = SpecifiedDirection.fromParent(topDir, e.dir)
val dirString = resolvedDir match {
- case UserDirection.Unspecified | UserDirection.Output => "output"
- case UserDirection.Flip | UserDirection.Input => "input"
+ case SpecifiedDirection.Unspecified | SpecifiedDirection.Output => "output"
+ case SpecifiedDirection.Flip | SpecifiedDirection.Input => "input"
}
val clearDir = resolvedDir match {
- case UserDirection.Input | UserDirection.Output => true
- case UserDirection.Unspecified | UserDirection.Flip => false
+ case SpecifiedDirection.Input | SpecifiedDirection.Output => true
+ case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false
}
s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}"
}
@@ -35,23 +35,23 @@ private class Emitter(circuit: Circuit) {
case d: Vec[_] => s"${emitType(d.sample_element, clearDir)}[${d.length}]"
case d: Record => {
val childClearDir = clearDir ||
- d.userDirection == UserDirection.Input || d.userDirection == UserDirection.Output
+ d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output
def eltPort(elt: Data): String = (childClearDir, firrtlUserDirOf(elt)) match {
case (true, _) =>
s"${elt.getRef.name} : ${emitType(elt, true)}"
- case (false, UserDirection.Unspecified | UserDirection.Output) =>
+ case (false, SpecifiedDirection.Unspecified | SpecifiedDirection.Output) =>
s"${elt.getRef.name} : ${emitType(elt, false)}"
- case (false, UserDirection.Flip | UserDirection.Input) =>
+ case (false, SpecifiedDirection.Flip | SpecifiedDirection.Input) =>
s"flip ${elt.getRef.name} : ${emitType(elt, false)}"
}
d.elements.toIndexedSeq.reverse.map(e => eltPort(e._2)).mkString("{", ", ", "}")
}
}
- private def firrtlUserDirOf(d: Data): UserDirection = d match {
+ private def firrtlUserDirOf(d: Data): SpecifiedDirection = d match {
case d: Vec[_] =>
- UserDirection.fromParent(d.userDirection, firrtlUserDirOf(d.sample_element))
- case d => d.userDirection
+ SpecifiedDirection.fromParent(d.specifiedDirection, firrtlUserDirOf(d.sample_element))
+ case d => d.specifiedDirection
}
private def emit(e: Command, ctx: Component): String = {