summaryrefslogtreecommitdiff
path: root/src/main
AgeCommit message (Expand)Author
2017-12-19Add WireInit.apply that accepts DontCare (#731)Jack Koenig
2017-12-14Fix a few compiler warnings (#738)Jack Koenig
2017-12-13Improve some of the ScalaDoc in chisel3.utilJack Koenig
2017-11-23Change switch to emit when, elsewhen, instead of when, when (#720)Jack Koenig
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
2017-10-26Invalidateapi (#645)Adam Izraelevitz
2017-10-05the cloneType and chiselCloneType hot mess 🔥 (#653)Richard Lin
2017-10-03Remove warning in Queue for compatibility code (#702)Jack Koenig
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-17More of the bindings refactor (#635)Richard Lin
2017-08-17Make Reset a trait (#672)Jack Koenig
2017-08-15Make .dir give correct direction for Module io in compatibilityJack Koenig
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-08-01Address scalastyle issues, out of date comments, extraneous imports. (#658)Jim Lawson
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-07-07Ensure IO is non-null before attempting to autoWrapPorts. (#643)Jim Lawson
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-05-31Add dontTouch for annotating Data to not be removedJack Koenig
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
2017-05-28Correct misleading example codeEdward Wang
2017-05-25Update internal Pipe wiring - fixes #615" (#616)Jim Lawson
2017-05-19Update comments describing Decoupled/ReadyValid - fix #437. (#493)Jim Lawson
2017-05-11Scope resources - move them down into chisel3 directory - fixes #549 (#610)Jim Lawson
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
2017-03-17Add single arg constructor back to compatibility reg (#553)Richard Lin
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Move log2Up and log2Down to compatibility wrapperAndrew Waterman
2017-03-08Improve UIntToOH behavior on incorrect inputs; avoid log2UpAndrew Waterman
2017-03-08In OHToUInt, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-08Add Analog typeJack Koenig
2017-02-07Name all the thingsducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-30Add shift register with reset (#439)Stevo
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 19:01:50 +0000