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authorAndrew Waterman2017-02-24 00:17:05 -0800
committerJack Koenig2017-03-08 11:27:04 -0600
commitd4ecf002be3490e27a1cd50bd00a12837beaffb1 (patch)
treec77f4447b53b5f8b43cc9f75508aa14e4b8533f0 /src/main
parent96a24d4ba2805ef291ed25047fd31de7131e8311 (diff)
Use zero-width wire for 1-entry enum
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/util/Enum.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 45aee62a..a3e39047 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -10,7 +10,7 @@ import chisel3._
trait Enum {
/** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
protected def createValues(n: Int): Seq[UInt] =
- (0 until n).map(_.U(log2Up(n).W))
+ (0 until n).map(_.U(log2Ceil(n).W))
/** Returns n unique UInt values, use with unpacking to specify an enumeration.
*