From d4ecf002be3490e27a1cd50bd00a12837beaffb1 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 24 Feb 2017 00:17:05 -0800
Subject: Use zero-width wire for 1-entry enum

---
 src/main/scala/chisel3/util/Enum.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 45aee62a..a3e39047 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -10,7 +10,7 @@ import chisel3._
 trait Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
   protected def createValues(n: Int): Seq[UInt] =
-    (0 until n).map(_.U(log2Up(n).W))
+    (0 until n).map(_.U(log2Ceil(n).W))
 
   /** Returns n unique UInt values, use with unpacking to specify an enumeration.
     *
-- 
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