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AgeCommit message (Expand)Author
2017-12-22Fixes format strings in assertions. Fixes #540 (#542)Jack Koenig
2017-12-20Add compileOptions to Module.apply, use for invalidating submod ports (#747)Jack Koenig
2017-12-19Properly invalidate submodule IOs in tests (#745)Jack Koenig
2017-12-19Add WireInit.apply that accepts DontCare (#731)Jack Koenig
2017-12-19Add source info / compile options transforms to Mem accessors (#744)Richard Lin
2017-12-14Fix a few compiler warnings (#738)Jack Koenig
2017-12-14Add error message for <> of Vec and Seq of different lengths (#739)Jack Koenig
2017-12-13Improve some of the ScalaDoc in chisel3.utilJack Koenig
2017-12-08Reject negative shift amounts; add tests (#730)Andrew Waterman
2017-11-23Change switch to emit when, elsewhen, instead of when, when (#720)Jack Koenig
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
2017-11-06Update InvalidateAPISpec tests. (#714)Jim Lawson
2017-10-26Invalidateapi (#645)Adam Izraelevitz
2017-10-05the cloneType and chiselCloneType hot mess 🔥 (#653)Richard Lin
2017-10-03Remove warning in Queue for compatibility code (#702)Jack Koenig
2017-09-26Disallow assignment to op results (#698)Richard Lin
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-17More of the bindings refactor (#635)Richard Lin
2017-08-17Make Reset a trait (#672)Jack Koenig
2017-08-15Make .dir give correct direction for Module io in compatibilityJack Koenig
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-08-08Give default direction to children of Vecs in compatibility codeJack Koenig
2017-08-07Don't assign default direction to Analog in Chisel._Jack Koenig
2017-08-01Address scalastyle issues, out of date comments, extraneous imports. (#658)Jim Lawson
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-07-28Add rebinding test (#654)Richard Lin
2017-07-27Fix style of literal creators (#637)Chick Markley
2017-07-07Ensure IO is non-null before attempting to autoWrapPorts. (#643)Jim Lawson
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-05-31Add dontTouch for annotating Data to not be removedJack Koenig
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
2017-05-28Correct misleading example codeEdward Wang
2017-05-25Support updated scalatest/scalacheck; bump sbt and Scala versions. (#605)Jim Lawson
2017-05-25Update internal Pipe wiring - fixes #615" (#616)Jim Lawson
2017-05-19Update comments describing Decoupled/ReadyValid - fix #437. (#493)Jim Lawson
2017-05-11Scope resources - move them down into chisel3 directory - fixes #549 (#610)Jim Lawson
2017-05-10Add implicit CompileOptions to Record and Bundle (#595)Jack Koenig
2017-05-04Connecting basic types wrong should error in chisel (#497)Chick Markley
2017-05-03Clear clock and reset scope for RawModule (#607)Richard Lin
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-15 Fix assignment from 0-entry Vec: add test (#580)Andrew Waterman
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
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