diff options
| author | Richard Lin | 2017-10-05 12:13:27 -0700 |
|---|---|---|
| committer | GitHub | 2017-10-05 12:13:27 -0700 |
| commit | 8168a8eea6c3465966081c5acd0347e09791361c (patch) | |
| tree | 23fc79aaaeb512b445748dd78dbb5ce3bb67e372 /src | |
| parent | 0f1b64173c305f5d36e4c84a8e575ff6f997b359 (diff) | |
the cloneType and chiselCloneType hot mess 🔥 (#653)
Addresses #419
cloneType is now marked (through comments only) as an internal API.
chiselCloneType deprecated (and changed to cloneTypeFull internally, analogous to cloneTypeWidth).
chiselTypeOf(data) introduced as the external API to get a chisel type from a hardware object
Intended usage: cloning is an implementation detail, and chisel types and hardware objects both should act as immutable types, with operations like Input(...), Reg(...), etc returning a copy and leaving the original unchanged. Hence, the clone operations are all deprecated.
Deletes what appears to be an unused Bundle companion object.
Input(...), Output(...), Flipped(...) require the object to be unbound
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 2 |
6 files changed, 18 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index f181caba..d65196d9 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -42,6 +42,12 @@ package object Chisel { // scalastyle:ignore package.object.name } } } + implicit class cloneTypeable[T <: Data](val target: T) extends AnyVal { + import chisel3.core.DataMirror + def chiselCloneType: T = { + DataMirror.internal.chiselTypeClone(target).asInstanceOf[T] + } + } type ChiselException = chisel3.internal.ChiselException diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index ee77ba23..d335f1f1 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -19,6 +19,7 @@ package object chisel3 { // scalastyle:ignore package.object.name val Input = chisel3.core.Input val Output = chisel3.core.Output val Flipped = chisel3.core.Flipped + val chiselTypeOf = chisel3.core.chiselTypeOf type Data = chisel3.core.Data object Wire extends chisel3.core.WireFactory { @@ -56,6 +57,13 @@ package object chisel3 { // scalastyle:ignore package.object.name } } + implicit class cloneTypeable[T <: Data](val target: T) extends AnyVal { + @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") + def chiselCloneType: T = { + target.cloneTypeFull.asInstanceOf[T] + } + } + type Aggregate = chisel3.core.Aggregate object Vec extends chisel3.core.VecFactory { import scala.language.experimental.macros diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index ef09c07d..451fd039 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -281,7 +281,7 @@ object Queue entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { - val q = Module(new Queue(enq.bits.cloneType, entries, pipe, flow)) + val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow)) q.io.enq.valid := enq.valid // not using <> so that override is allowed q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 34c4d6d8..34d22a07 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -8,8 +8,7 @@ object RegEnable { /** Returns a register with the specified next, update enable gate, and no reset initialization. */ def apply[T <: Data](next: T, enable: Bool): T = { - val clonedNext = next.chiselCloneType - val r = Reg(clonedNext) + val r = Reg(chiselTypeOf(next)) when (enable) { r := next } r } diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 432cd278..e84e6a02 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { class ModuleWire extends Module { val io = IO(new SimpleIO) - val inc = Wire(Module(new PlusOne).io.chiselCloneType) + val inc = Wire(chiselTypeOf(Module(new PlusOne).io)) inc.in := io.in io.out := inc.out } diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 9b8855c4..6c62ab26 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -145,7 +145,7 @@ class ZeroEntryVecTester extends BasicTester { require(bundleWithZeroEntryVec.asUInt.getWidth == 1) val m = Module(new Module { - val io = IO(Output(bundleWithZeroEntryVec.cloneType)) + val io = IO(Output(bundleWithZeroEntryVec)) }) WireInit(m.io.bar) |
