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authorJack Koenig2017-12-14 15:04:50 -0800
committerGitHub2017-12-14 15:04:50 -0800
commitef1400f45404210121f53b38585602a8c7c2560e (patch)
tree22c989b6f42c9c206dd99d74e376dd95f81c4dd0 /src
parentc327dc328ca819031a086ae102fefe2909831e24 (diff)
Add error message for <> of Vec and Seq of different lengths (#739)
Fixes #482
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/chiselTests/Vec.scala22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 1c5157b5..08b9cdf5 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -252,4 +252,26 @@ class VecSpec extends ChiselPropSpec {
property("Dynamic indexing of a Vec of Module IOs should work") {
assertTesterPasses{ new ModuleIODynamicIndexTester(4) }
}
+
+ property("It should be possible to bulk connect a Vec and a Seq") {
+ elaborate(new Module {
+ val io = IO(new Bundle {
+ val out = Output(Vec(4, UInt(8.W)))
+ })
+ val seq = Seq.fill(4)(0.U)
+ io.out <> seq
+ })
+ }
+
+ property("Bulk connecting a Vec and Seq of different sizes should report a ChiselException") {
+ a [ChiselException] should be thrownBy {
+ elaborate(new Module {
+ val io = IO(new Bundle {
+ val out = Output(Vec(4, UInt(8.W)))
+ })
+ val seq = Seq.fill(5)(0.U)
+ io.out <> seq
+ })
+ }
+ }
}