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2020-10-26Added Force Name API (#1634)Adam Izraelevitz
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-21Make `-e` option work with ChiselStage methods (#1630)Schuyler Eldridge
* Fix `-e` option causing ChiselStage.emit* to error Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of `-e` ChiselStage behavior Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add test of `-e` ChiselStage behavior
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage`
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
Co-authored-by: Megan Wachs <megan@sifive.com>
2020-09-09Add new annotation for Chisel Circuit serialization (#1580)Jack Koenig
ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it is Unserializable. Also the --chisel-output-file is added to the ChiselCli. New phase AddSerializationAnnotations constructs a CircuitSerializationAnnotation from ChiselCircuitAnnotation and ChiselOutputFileAnnotation. Both .fir and .pb file formats are supported. Default format is .fir unless a --chisel-output-file is specified with a .pb extension.
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
It shouldn't be removed until we also remove the underlying chisel3.Driver.
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ↵Schuyler Eldridge
ChiselStage$ helpers (#1566) * Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-20Remove use of PreservesAll, cleanup dependencies (#1558)Schuyler Eldridge
Remove usages of the deprecated trait PreservesAll and use an explicit false invalidates. Additionally, all phases are converted to be more canonical in there specification of dependencies by: 1. Overriding all default dependency implementations 2. Using def instead of val Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-13Move treadle dependency to the tests (#1554)Jack Koenig
Use inheritance to make TesterDriver Backend API extensible, then define a TreadleBackend in the test project
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
* Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-11Restore Counter.n API (#1546)Jack Koenig
Includes special case support for Counter(0) which has identical behavior to Counter(1) except for the value of n.
2020-08-06Update OneHot.scala (#1539)Leigang Kou
comment fix only.
2020-07-31Add emitSystemVerilog method to ChiselStage (#1534)Tom Alcorn
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
* Add positive range generator * Allow the Counter module to be instantiated with a Scala range * Use head/last to determine counter width Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * Let counter overflow naturally when appropriate We only need to explicitly wrap counters that don't start at zero, or end on a power of two. Otherwise we just let the counter overflow naturally to avoid wasting an extra mux. * Require counter range to be non-empty Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above. Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-28Select: update to work with records (#1525)Albert Chen
2020-07-25Using TreadleTesterPhase now requires new (#1520)Chick Markley
Treadle tester phase requires new to fix problems found when running tests in parallel.
2020-07-22Basic model checking API (#1499)Tom Alcorn
* Add `check(...)` affordance * Add assert (renamed from check and fixed) * Add verification statements * Move formal to experimental.verification * Make test use ChiselStage `generateFirrtl` has been cut from Chisel * Fix newly introduced style warnings * Fix some old style warnings for good measure * Revert "Fix some old style warnings for good measure" This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890. * Cut scalastyle comments * Cut formal delimiter comments
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-29- A few final fixes after the rebasechick
2020-06-29This adds a mechanism for the unittests to be run with the TreadleBackendchick
This mechanism is not enabled and should not change the behavior of existing tests A following PR will deliver a switch that will allow changing the backend. The reasons for this PR - Treadle tests run much faster, enabling quicker debugging and CI cycles - This will help ensure fidelity of Treadle to the Verilator backend A few tests are marked as verilator only due to black box limitations Change treadle to a direct dependency I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that regular compile have access to treadle Oops, made treadle the default A number of changes in response to @ducky64 review - made backend check clearer and add error handling for multiple backends specified - Fixed duplicate TargetDirAnnotation uses in Treadle backend - Cleaned up BlackBox test formatting - Undid unnecessary debugging changes from Counter - Undid .gitignore change, that should be on another PR A number of changes in response to @ducky64 review - Undid debugging changes made to BitWiseOps
2020-06-24Add missing finishWrapper call in TesterDriver (#1496)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-22Code simplification in internal Chisel._ methodSchuyler Eldridge
Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Deprecate Driver Execution classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Remove Driver usage from Chisel._ packageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Remove Driver usage in EmitterSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Canonicalize construction of Decoupled with no payload (#785)Jack Koenig
* Canonicalize construction of empty Decoupled * Change signature after dev meeting discussion * Make EmptyBundle private and final * Add test case for Decoupled with no payload * Apply suggestions from code review Co-authored-by: Richard Lin <richard.lin@berkeley.edu> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Richard Lin <richard.lin@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-19Memoize the hashcode of the ChiselCircuitAnnotation (#1485)Jack Koenig
2020-06-16Move Deprecated LFSR16 to CompatibilitySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
* Added group chisel API * Removed println * Added scaladoc * Added more tests * Cleaned spacing and removed println Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Fix double elaborationSchuyler Eldridge
Remove the requirement that FirrtlStage runs elaboration (this should be implicit) and remove the unneeded invalidation of elaboration by the Emitter. Due to Convert currently NOT invalidating Elaborate (when it should), add an optionalPrerequisiteOf to ensure that the Emitter runs before the Convert phase. Co-authored-by: David Biancolin <david.biancolin@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Expose ChiselStage's PhaseManager, rm extra wrapsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Mux1H: note results unspecified unless exactly one select signal is high (#1397)John Ingalls
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
2020-04-16Revert "Make uselessly public fields in utils private" (#1417)Adam Izraelevitz
This reverts commit c279860c36a73984cd1b7b0ac6c213e8b44a7143.
2020-04-10Make Counter emit valid FIRRTL (#1408)Jack Koenig
Remove var from object Counter.apply, using a Wire instead. Also improve some ScalaDoc and the class Counter require message.
2020-03-30Java API Documents Linking (#1367)Schuyler Eldridge
* Show linking against Javadoc Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add sbt-api-mappings plugin This adds the sbt-api-mappings plugin which enables auto-linking (properly setting the apiMappings for the sbt project) so that Scaldoc/unidoc generation will now automatically link against Java and Scala API docs (and use the right version). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Show linking against Scala APIs Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-26Set StageError cause in ChiselStage (#1382)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-03-24Propagate user compile options for Chisel.Module (#1387)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-24Add helper methods to ChiselStage for Driver migrationSchuyler Eldridge
This adds three new methods to ChiselStage to replace deprecated methods in the Driver for converting a Chisel circuit to a string: - emitChirrtl - emitFirrtl - emitVerilog This also adds a ChiselStage companion object that lets you generated a Chisel Circuit or a FIRRTL Circuit from a Chisel module: - elaborate - convert Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add string emission helper methods to ChiselStage
2020-03-24Deprecate Driver methods in favor of ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Wrap elaboration in ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Wrap elaboration in ChiselException
2020-03-02Cleanup aspects (#1359)Adam Izraelevitz
* Clean up aspects * Refactored InjectingAspect with InjectorAspect * Made AspectLibrary work with objects * Cleaned up code * Apply suggestions from code review * Added tests, removed deprecated newInstance call * Backed out removal of newInstance as exceptions were different * Removed trailing commas
2020-02-19Migrate to Dependency WrapperSchuyler Eldridge
This changes Phase dependency specification to use the new Dependency wrapper. Previously, dependencies were specified as classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
Close #1134
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