summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3
diff options
context:
space:
mode:
authorSchuyler Eldridge2020-06-16 15:50:39 -0400
committerSchuyler Eldridge2020-06-16 15:50:39 -0400
commit818ecf08be3042a33684b269fa849105744a8b09 (patch)
treeb03c1b4e3b29ba25ae8b74ac3d39da54dcb7bce6 /src/main/scala/chisel3
parent5271e89c09653fe0d38adf75b5bef1fe5d3539d2 (diff)
Move Deprecated LFSR16 to Compatibility
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/chisel3')
-rw-r--r--src/main/scala/chisel3/compatibility.scala36
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala46
2 files changed, 35 insertions, 47 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 9584fad6..0c4c18a9 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -4,6 +4,8 @@
* while moving to the more standard package naming convention `chisel3` (lowercase c).
*/
import chisel3._ // required for implicit conversions.
+import chisel3.experimental.chiselName
+import chisel3.util.random.FibonacciLFSR
package object Chisel { // scalastyle:ignore package.object.name number.of.types number.of.methods
import chisel3.internal.firrtl.Width
@@ -561,7 +563,39 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t
}
}
- val LFSR16 = chisel3.util.LFSR16
+ /** LFSR16 generates a 16-bit linear feedback shift register, returning the register contents.
+ * This is useful for generating a pseudo-random sequence.
+ *
+ * The example below, taken from the unit tests, creates two 4-sided dice using `LFSR16` primitives:
+ * @example {{{
+ * val bins = Reg(Vec(8, UInt(32.W)))
+ *
+ * // Create two 4 sided dice and roll them each cycle.
+ * // Use tap points on each LFSR so values are more independent
+ * val die0 = Cat(Seq.tabulate(2) { i => LFSR16()(i) })
+ * val die1 = Cat(Seq.tabulate(2) { i => LFSR16()(i + 2) })
+ *
+ * val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit.
+ *
+ * bins(rollValue) := bins(rollValue) + 1.U
+ *
+ * }}}
+ */
+ // scalastyle:off magic.number
+ object LFSR16 {
+ /** Generates a 16-bit linear feedback shift register, returning the register contents.
+ * @param increment optional control to gate when the LFSR updates.
+ */
+ @chiselName
+ def apply(increment: Bool = true.B): UInt =
+ VecInit( FibonacciLFSR
+ .maxPeriod(16, increment, seed = Some(BigInt(1) << 15))
+ .asBools
+ .reverse )
+ .asUInt
+
+ }
+ // scalastyle:on magic.number
val ListLookup = chisel3.util.ListLookup
val Lookup = chisel3.util.Lookup
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
deleted file mode 100644
index 5fc778fb..00000000
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ /dev/null
@@ -1,46 +0,0 @@
-// See LICENSE for license details.
-
-/** LFSRs in all shapes and sizes.
- */
-
-package chisel3.util
-
-import chisel3._
-import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
-import chisel3.util.random.FibonacciLFSR
-
-/** LFSR16 generates a 16-bit linear feedback shift register, returning the register contents.
- * This is useful for generating a pseudo-random sequence.
- *
- * The example below, taken from the unit tests, creates two 4-sided dice using `LFSR16` primitives:
- * @example {{{
- * val bins = Reg(Vec(8, UInt(32.W)))
- *
- * // Create two 4 sided dice and roll them each cycle.
- * // Use tap points on each LFSR so values are more independent
- * val die0 = Cat(Seq.tabulate(2) { i => LFSR16()(i) })
- * val die1 = Cat(Seq.tabulate(2) { i => LFSR16()(i + 2) })
- *
- * val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit.
- *
- * bins(rollValue) := bins(rollValue) + 1.U
- *
- * }}}
- */
-// scalastyle:off magic.number
-@deprecated("LFSR16 is deprecated in favor of the parameterized chisel3.util.random.LFSR", "3.2")
-object LFSR16 {
- /** Generates a 16-bit linear feedback shift register, returning the register contents.
- * @param increment optional control to gate when the LFSR updates.
- */
- @deprecated("Use chisel3.util.random.LFSR(16) for a 16-bit LFSR", "3.2")
- @chiselName
- def apply(increment: Bool = true.B): UInt =
- VecInit( FibonacciLFSR
- .maxPeriod(16, increment, seed = Some(BigInt(1) << 15))
- .asBools
- .reverse )
- .asUInt
-
-}
-// scalastyle:on magic.number