diff options
| author | Albert Chen | 2020-09-15 13:50:29 -0700 |
|---|---|---|
| committer | GitHub | 2020-09-15 13:50:29 -0700 |
| commit | c613c285c3e044370024a1b5cc0a0da1dbc3e5e6 (patch) | |
| tree | d41427e2be643d80717df6d286c1cbc94ff0db2f /src/main/scala/chisel3 | |
| parent | b4f2b7acb2ea69dac116efed3ff873356d14b015 (diff) | |
make parameters for util modules public (#1452)
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index e8c4ea8f..056279e0 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -101,7 +101,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T * }}} */ @chiselName -class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) +class RRArbiter[T <: Data](val gen: T, val n: Int) extends LockingRRArbiter[T](gen, n, 1) /** Hardware module that is used to sequence n producers into 1 consumer. * Priority is given to lower producer. @@ -117,7 +117,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) * }}} */ @chiselName -class Arbiter[T <: Data](gen: T, n: Int) extends Module { +class Arbiter[T <: Data](val gen: T, val n: Int) extends Module { val io = IO(new ArbiterIO(gen, n)) io.chosen := (n-1).asUInt diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 884235bf..ade93717 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -194,10 +194,10 @@ class QueueIO[T <: Data](private val gen: T, val entries: Int) extends Bundle * }}} */ @chiselName -class Queue[T <: Data](gen: T, +class Queue[T <: Data](val gen: T, val entries: Int, - pipe: Boolean = false, - flow: Boolean = false) + val pipe: Boolean = false, + val flow: Boolean = false) (implicit compileOptions: chisel3.CompileOptions) extends Module() { require(entries > -1, "Queue must have non-negative number of entries") diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index ef27263e..1bd398f2 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -168,7 +168,7 @@ object Pipe { * @see [[Queue]] and the [[Queue$ Queue factory]] for actual queues * @see The [[ShiftRegister$ ShiftRegister factory]] to generate a pipe without a [[Valid]] interface */ -class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { +class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { /** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output * @define notAQueue |