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-rw-r--r--src/main/scala/chisel3/util/Valid.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index ef27263e..1bd398f2 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -168,7 +168,7 @@ object Pipe {
* @see [[Queue]] and the [[Queue$ Queue factory]] for actual queues
* @see The [[ShiftRegister$ ShiftRegister factory]] to generate a pipe without a [[Valid]] interface
*/
-class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module {
+class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module {
/** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output
* @define notAQueue