diff options
| author | Albert Chen | 2020-09-15 13:50:29 -0700 |
|---|---|---|
| committer | GitHub | 2020-09-15 13:50:29 -0700 |
| commit | c613c285c3e044370024a1b5cc0a0da1dbc3e5e6 (patch) | |
| tree | d41427e2be643d80717df6d286c1cbc94ff0db2f /src/main/scala/chisel3/util/Valid.scala | |
| parent | b4f2b7acb2ea69dac116efed3ff873356d14b015 (diff) | |
make parameters for util modules public (#1452)
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index ef27263e..1bd398f2 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -168,7 +168,7 @@ object Pipe { * @see [[Queue]] and the [[Queue$ Queue factory]] for actual queues * @see The [[ShiftRegister$ ShiftRegister factory]] to generate a pipe without a [[Valid]] interface */ -class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { +class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { /** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output * @define notAQueue |