From c613c285c3e044370024a1b5cc0a0da1dbc3e5e6 Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Tue, 15 Sep 2020 13:50:29 -0700 Subject: make parameters for util modules public (#1452) Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/Valid.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/util/Valid.scala') diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index ef27263e..1bd398f2 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -168,7 +168,7 @@ object Pipe { * @see [[Queue]] and the [[Queue$ Queue factory]] for actual queues * @see The [[ShiftRegister$ ShiftRegister factory]] to generate a pipe without a [[Valid]] interface */ -class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { +class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module { /** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output * @define notAQueue -- cgit v1.2.3