Switch to HowToSerialize for Emission (#1405)

* Fix emit{Firrtl,Verilog} for CustomFileEmission

Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Use CustomFileEmission for ChiselCircuitAnnotation

Removes the explicit chisel3.phases.Emitter and instead does emission
with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then
prevents the need for passing around DeletedAnnotations. As a
consequence, I removed an unnecessary run of a second Converter in the
Driver.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fix tests for use of CustomFileEmission trait

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fixes for newer CustomFileEmission API

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

5 files changed, 44 insertions, 24 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 7393fd22..0e1389c2 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -231,7 +231,8 @@ object Driver extends BackendCompilationUtilities {
            Dependency[DriverCompatibility.FirrtlPreprocessing],
            Dependency[chisel3.stage.phases.MaybeFirrtlStage] )
     val currentState =
-      Seq( Dependency[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile] )
+      Seq( Dependency[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile],
+           Dependency[chisel3.stage.phases.Convert] )
 
     val phases: Seq[Phase] = new PhaseManager(targets, currentState) {
       override val wrappers = Seq( DeletedWrapper(_: Phase) )
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index e4906456..e4663dd4 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -3,20 +3,26 @@
 package chisel3.stage
 
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
-import firrtl.options.{HasShellOptions, OptionsException, ShellOption, Unserializable}
+import firrtl.options.{CustomFileEmission, HasShellOptions, OptionsException, ShellOption, StageOptions, Unserializable}
+import firrtl.options.Viewer.view
 import chisel3.{ChiselException, Module}
 import chisel3.RawModule
 import chisel3.internal.Builder
-import chisel3.internal.firrtl.Circuit
+import chisel3.internal.firrtl.{Circuit, Emitter => OldEmitter}
 import firrtl.AnnotationSeq
+import java.io.File
 
 /** Mixin that indicates that this is an [[firrtl.annotations.Annotation]] used to generate a [[ChiselOptions]] view.
   */
-sealed trait ChiselOption extends Unserializable { this: Annotation => }
+sealed trait ChiselOption { this: Annotation => }
 
 /** Disable the execution of the FIRRTL compiler by Chisel
   */
-case object NoRunFirrtlCompilerAnnotation extends NoTargetAnnotation with ChiselOption with HasShellOptions {
+case object NoRunFirrtlCompilerAnnotation
+    extends NoTargetAnnotation
+    with ChiselOption
+    with HasShellOptions
+    with Unserializable {
 
   val options = Seq(
     new ShellOption[Unit](
@@ -29,7 +35,11 @@ case object NoRunFirrtlCompilerAnnotation extends NoTargetAnnotation with Chisel
 
 /** On an exception, this will cause the full stack trace to be printed as opposed to a pruned stack trace.
   */
-case object PrintFullStackTraceAnnotation extends NoTargetAnnotation with ChiselOption with HasShellOptions {
+case object PrintFullStackTraceAnnotation
+    extends NoTargetAnnotation
+    with ChiselOption
+    with HasShellOptions
+    with Unserializable {
 
   val options = Seq(
     new ShellOption[Unit](
@@ -90,14 +100,26 @@ object ChiselGeneratorAnnotation extends HasShellOptions {
 /** Stores a Chisel Circuit
   * @param circuit a Chisel Circuit
   */
-case class ChiselCircuitAnnotation(circuit: Circuit) extends NoTargetAnnotation with ChiselOption {
+case class ChiselCircuitAnnotation(circuit: Circuit)
+    extends NoTargetAnnotation
+    with ChiselOption
+    with CustomFileEmission {
   /* Caching the hashCode for a large circuit is necessary due to repeated queries.
    * Not caching the hashCode will cause severe performance degredations for large [[Circuit]]s.
    */
   override lazy val hashCode: Int = circuit.hashCode
+
+  protected def baseFileName(annotations: AnnotationSeq): String = {
+    view[ChiselOptions](annotations).outputFile.getOrElse(circuit.name)
+  }
+
+  protected def suffix: Option[String] = Some(".fir")
+
+  override def getBytes: Iterable[Byte] = OldEmitter.emit(circuit).getBytes
+
 }
 
-case class ChiselOutputFileAnnotation(file: String) extends NoTargetAnnotation with ChiselOption
+case class ChiselOutputFileAnnotation(file: String) extends NoTargetAnnotation with ChiselOption with Unserializable
 
 object ChiselOutputFileAnnotation extends HasShellOptions {
 
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index ec53757f..ac3553b9 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -3,7 +3,6 @@
 package chisel3.stage
 
 import firrtl.{ir => fir, AnnotationSeq, EmittedFirrtlCircuitAnnotation, EmittedVerilogCircuitAnnotation}
-import firrtl.annotations.DeletedAnnotation
 import firrtl.options.{Dependency, Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain}
 import firrtl.options.phases.DeletedWrapper
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlCli}
@@ -23,7 +22,6 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
          Dependency[chisel3.stage.phases.AddImplicitOutputFile],
          Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
          Dependency[chisel3.stage.phases.MaybeAspectPhase],
-         Dependency[chisel3.stage.phases.Emitter],
          Dependency[chisel3.stage.phases.Convert],
          Dependency[chisel3.stage.phases.MaybeFirrtlStage] )
 
@@ -60,12 +58,15 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
     args: Array[String] = Array.empty,
     annotations: AnnotationSeq = Seq.empty): String = {
 
-    execute(Array("-X", "none") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
+    val annos = execute(Array("--no-run-firrtl") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
+
+    annos
       .collectFirst {
-        case DeletedAnnotation(_, EmittedFirrtlCircuitAnnotation(a)) => a
+        case a: ChiselCircuitAnnotation => a.getBytes
       }
       .get
-      .value
+      .map(_.toChar)
+      .mkString
 
   }
 
@@ -82,7 +83,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
 
     execute(Array("-X", "high") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
       .collectFirst {
-        case DeletedAnnotation(_, EmittedFirrtlCircuitAnnotation(a)) => a
+        case EmittedFirrtlCircuitAnnotation(a) => a
       }
       .get
       .value
@@ -102,7 +103,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
 
     execute(Array("-X", "verilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
       .collectFirst {
-        case DeletedAnnotation(_, EmittedVerilogCircuitAnnotation(a)) => a
+        case EmittedVerilogCircuitAnnotation(a) => a
       }
       .get
       .value
@@ -121,7 +122,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
 
     execute(Array("-X", "sverilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
       .collectFirst {
-        case DeletedAnnotation(_, EmittedVerilogCircuitAnnotation(a)) => a
+        case EmittedVerilogCircuitAnnotation(a) => a
       }
       .get
       .value
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala
index 57766be6..079e3f22 100644
--- a/src/main/scala/chisel3/stage/package.scala
+++ b/src/main/scala/chisel3/stage/package.scala
@@ -3,11 +3,9 @@
 package chisel3
 
 import firrtl._
-import firrtl.annotations.DeletedAnnotation
 import firrtl.options.OptionsView
 
 import chisel3.internal.firrtl.{Circuit => ChiselCircuit}
-import chisel3.stage.phases.{Convert, Emitter}
 
 package object stage {
 
@@ -28,17 +26,14 @@ package object stage {
 
   private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] {
 
-    lazy val dummyConvert = new Convert
-    lazy val dummyEmitter = new Emitter
-
     def view(options: AnnotationSeq): ChiselExecutionResult = {
       var chiselCircuit: Option[ChiselCircuit] = None
       var chirrtlCircuit: Option[String] = None
 
       options.foreach {
-        case DeletedAnnotation(dummyConvert.name, ChiselCircuitAnnotation(a)) => chiselCircuit = Some(a)
-        case DeletedAnnotation(dummyEmitter.name, EmittedFirrtlCircuitAnnotation(EmittedFirrtlCircuit(_, a, _))) =>
-          chirrtlCircuit = Some(a)
+        case a@ ChiselCircuitAnnotation(b) =>
+          chiselCircuit = Some(b)
+          chirrtlCircuit = Some(a.getBytes.map(_.toChar).mkString)
         case _ =>
       }
 
diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala
index 54ea6963..0ba1a5c9 100644
--- a/src/main/scala/chisel3/stage/phases/Convert.scala
+++ b/src/main/scala/chisel3/stage/phases/Convert.scala
@@ -20,6 +20,7 @@ class Convert extends Phase with PreservesAll[Phase] {
 
   def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {
     case a: ChiselCircuitAnnotation =>
+      Some(a) ++
       /* Convert this Chisel Circuit to a FIRRTL Circuit */
       Some(FirrtlCircuitAnnotation(Converter.convert(a.circuit))) ++
       /* Convert all Chisel Annotations to FIRRTL Annotations */