Delete outdated scalastyle configuration comments from source

11 files changed, 31 insertions, 37 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 6ac0a5c1..7393fd22 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -211,7 +211,7 @@ object Driver extends BackendCompilationUtilities {
     * @return                       An execution result with useful stuff, or failure with message
     */
   @deprecated("Use chisel3.stage.ChiselStage.execute. This will be removed in 3.4.", "3.2.2")
-  def execute( // scalastyle:ignore method.length
+  def execute(
       optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions,
       dut: () => RawModule): ChiselExecutionResult = {
 
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 89aefef2..d63a8343 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -8,7 +8,7 @@ import chisel3.experimental.chiselName
 import chisel3.util.random.FibonacciLFSR
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage, phases}
 
-package object Chisel {     // scalastyle:ignore package.object.name number.of.types number.of.methods
+package object Chisel {
   import chisel3.internal.firrtl.Width
 
   import scala.language.experimental.macros
@@ -207,8 +207,8 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     /** Create an SInt literal with specified width. */
     def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
-    def Lit(value: BigInt): SInt = value.asSInt // scalastyle:ignore method.name
-    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W) // scalastyle:ignore method.name
+    def Lit(value: BigInt): SInt = value.asSInt
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
     def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
@@ -263,7 +263,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
   abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.BlackBox(params) {
     // This class auto-wraps the BlackBox with IO(...), allowing legacy code (where IO(...) wasn't
     // required) to build.
-    override def _compatAutoWrapPorts(): Unit = { // scalastyle:ignore method.name
+    override def _compatAutoWrapPorts(): Unit = {
       if (!_compatIoPortBound()) {
         _bindIoInPlace(io)
       }
@@ -322,7 +322,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
       this(Option(_clock), Option(_reset))(moduleCompileOptions)
 
-    override def _compatAutoWrapPorts(): Unit = { // scalastyle:ignore method.name
+    override def _compatAutoWrapPorts(): Unit = {
       if (!_compatIoPortBound() && io != null) {
         _bindIoInPlace(io)
       }
@@ -426,7 +426,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
   }
 
   @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-  object debug {  // scalastyle:ignore object.name
+  object debug {
     def apply (arg: Data): Data = arg
   }
 
@@ -439,7 +439,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     }
   }
 
-  object testers {    // scalastyle:ignore object.name
+  object testers {
     type BasicTester = chisel3.testers.BasicTester
     val TesterDriver = chisel3.testers.TesterDriver
   }
@@ -593,7 +593,6 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     *
     * }}}
     */
-  // scalastyle:off magic.number
   object LFSR16 {
     /** Generates a 16-bit linear feedback shift register, returning the register contents.
       * @param increment optional control to gate when the LFSR updates.
@@ -607,7 +606,6 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
         .asUInt
 
   }
-  // scalastyle:on magic.number
 
   val ListLookup = chisel3.util.ListLookup
   val Lookup = chisel3.util.Lookup
@@ -636,12 +634,12 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     * Because its contents won't necessarily have the same level of stability and support as
     * non-experimental, you must explicitly import this package to use its contents.
     */
-  object experimental {  // scalastyle:ignore object.name
+  object experimental {
     import scala.annotation.compileTimeOnly
 
-    class dump extends chisel3.internal.naming.dump  // scalastyle:ignore class.name
-    class treedump extends chisel3.internal.naming.treedump  // scalastyle:ignore class.name
-    class chiselName extends chisel3.internal.naming.chiselName  // scalastyle:ignore class.name
+    class dump extends chisel3.internal.naming.dump
+    class treedump extends chisel3.internal.naming.treedump
+    class chiselName extends chisel3.internal.naming.chiselName
   }
 
   implicit class DataCompatibility(a: Data) {
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 2124fa25..be8d8f2f 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -25,7 +25,7 @@ private class Emitter(circuit: Circuit) {
     s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}"
   }
 
-  private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit
+  private def emitType(d: Data, clearDir: Boolean = false): String = d match {
     case d: Clock => "Clock"
     case _: AsyncReset => "AsyncReset"
     case _: ResetType => "Reset"
@@ -62,15 +62,15 @@ private class Emitter(circuit: Circuit) {
     case d => d.specifiedDirection
   }
 
-  private def emit(e: Command, ctx: Component): String = { // scalastyle:ignore cyclomatic.complexity
+  private def emit(e: Command, ctx: Component): String = {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
       case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit
+      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
-      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit
+      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
       case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
       case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
@@ -101,7 +101,6 @@ private class Emitter(circuit: Circuit) {
         s"skip"
     }
     firrtlLine + e.sourceInfo.makeMessage(" " + _)
-    // scalastyle:on line.size.limit
   }
 
   private def emitParam(name: String, p: Param): String = {
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 2dbb5b9d..938f0250 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -45,7 +45,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
       Predef
         .augmentString(stackTrace)
         .lines
-        .foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex
+        .foreach(line => println(s"${ErrorLog.errTag} $line"))
       throw new StageError(cause=ce)
   }
 
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 6231f81a..6e414ff4 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -16,7 +16,6 @@ import treadle.executable.StopException
 import treadle.stage.TreadleTesterPhase
 import treadle.{CallResetAtStartupAnnotation, TreadleTesterAnnotation, WriteVcdAnnotation}
 
-//scalastyle:off magic.number method.length
 object TesterDriver extends BackendCompilationUtilities {
   var MaxTreadleCycles = 10000L
 
@@ -125,7 +124,6 @@ object TesterDriver extends BackendCompilationUtilities {
     }
   }
 
-  //scalastyle:off cyclomatic.complexity method.length
   def executeTreadle(t:                    () => BasicTester,
                      additionalVResources: Seq[String] = Seq(),
                      annotations:          AnnotationSeq = Seq(),
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 7c0abdb2..27de9982 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -86,16 +86,16 @@ object BitPat {
     final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
 
     /** @group SourceInfoTransformMacro */
-    def do_=== (that: BitPat)  // scalastyle:ignore method.name
+    def do_=== (that: BitPat)
                (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
     /** @group SourceInfoTransformMacro */
-    def do_=/= (that: BitPat)  // scalastyle:ignore method.name
+    def do_=/= (that: BitPat)
                (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
 
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @chiselRuntimeDeprecated
     @deprecated("Use '=/=', which avoids potential precedence problems", "3.0")
-    def do_!= (that: BitPat)  // scalastyle:ignore method.name
+    def do_!= (that: BitPat)
               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x
   }
 }
@@ -115,12 +115,12 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou
   def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
 
   /** @group SourceInfoTransformMacro */
-  def do_=== (that: UInt)  // scalastyle:ignore method.name
+  def do_=== (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     value.asUInt === (that & mask.asUInt)
   }
   /** @group SourceInfoTransformMacro */
-  def do_=/= (that: UInt)  // scalastyle:ignore method.name
+  def do_=/= (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     !(this === that)
   }
@@ -128,7 +128,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou
   def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
   @chiselRuntimeDeprecated
   @deprecated("Use '=/=', which avoids potential precedence problems", "3.0")
-  def do_!= (that: UInt)  // scalastyle:ignore method.name
+  def do_!= (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     this =/= that
   }
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 4681b34a..3583b7d1 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -90,7 +90,7 @@ object Fill {
   * }}}
   */
 object Reverse {
-  private def doit(in: UInt, length: Int): UInt = length match { // scalastyle:ignore cyclomatic.complexity
+  private def doit(in: UInt, length: Int): UInt = length match {
     case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
     case _ if length <= 1 => in
     case _ if isPow2(length) && length >= 8 && length <= 64 =>
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 7aebc815..4938d075 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -12,7 +12,7 @@ import scala.reflect.macros.blackbox._
 import chisel3._
 
 @deprecated("The unless conditional is deprecated, use when(!condition){...} instead", "3.2")
-object unless {  // scalastyle:ignore object.name
+object unless {
   /** Does the same thing as [[when$ when]], but with the condition inverted.
     */
   def apply(c: Bool)(block: => Any) {
@@ -56,7 +56,7 @@ class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lit
   * @note dummy implementation, a macro inside [[switch]] transforms this into the actual
   * implementation
   */
-object is {   // scalastyle:ignore object.name
+object is {
   // TODO: Begin deprecation of non-type-parameterized is statements.
   /** Executes `block` if the switch condition is equal to any of the values in `v`.
     */
@@ -90,7 +90,7 @@ object is {   // scalastyle:ignore object.name
   * }
   * }}}
   */
-object switch {  // scalastyle:ignore object.name
+object switch {
   def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val q"..$body" = x
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 82511ee5..884235bf 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -107,7 +107,7 @@ object Decoupled
     */
   @chiselName
   def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
-    require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") // scalastyle:ignore line.size.limit
+    require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
     val d = Wire(new DecoupledIO(irr.bits))
     d.bits := irr.bits
     d.valid := irr.valid
@@ -138,7 +138,7 @@ object Irrevocable
     * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO
     */
   def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = {
-    require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") // scalastyle:ignore line.size.limit
+    require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.")
     val i = Wire(new IrrevocableIO(dec.bits))
     dec.bits := i.bits
     dec.valid := i.valid
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 3d14b5c2..92bfcde7 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -123,7 +123,6 @@ object loadMemoryFromFile {
   * Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does
   * not need this transform to do that.
   */
-//scalastyle:off method.length
 class LoadMemoryTransform extends Transform {
   def inputForm: CircuitForm  = LowForm
   def outputForm: CircuitForm = LowForm
diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala
index 5b67c509..17e10311 100644
--- a/src/main/scala/chisel3/util/random/LFSR.scala
+++ b/src/main/scala/chisel3/util/random/LFSR.scala
@@ -103,7 +103,7 @@ object LFSR {
   lazy val tapsMaxPeriod: Map[Int, Seq[Set[Int]]] = tapsFirst ++ tapsSecond
 
   /** First portion of known taps (a combined map hits the 64KB JVM method limit) */
-  private def tapsFirst = Map( // scalastyle:off magic.number
+  private def tapsFirst = Map(
     2    -> Seq(Set(2, 1)),
     3    -> Seq(Set(3, 2)),
     4    -> Seq(Set(4, 3)),
@@ -894,6 +894,6 @@ object LFSR {
     786  -> Seq(Set(786, 782, 780, 771)),
     1024 -> Seq(Set(1024, 1015, 1002, 1001)),
     2048 -> Seq(Set(2048, 2035, 2034, 2029)),
-    4096 -> Seq(Set(4096, 4095, 4081, 4069)) ) // scalastyle:on magic.number
+    4096 -> Seq(Set(4096, 4095, 4081, 4069)) )
 
 }