diff options
| author | Edward Wang | 2019-07-27 19:22:23 -0700 |
|---|---|---|
| committer | edwardcwang | 2020-02-10 16:38:43 -0500 |
| commit | 1cfa9c1df3d91a99ad146f85c77cee7c37a3a116 (patch) | |
| tree | e40715ffe25c4443582893c4c4bfec6aa0000496 /src/main/scala/chisel3 | |
| parent | 9a209b82022a18542260715bc7db777f68ab079f (diff) | |
Make Queue.irrevocable work properly in chisel3
Close #1134
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c20c1eb3..0ed6984b 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -305,7 +305,7 @@ object Queue flow: Boolean = false): IrrevocableIO[T] = { val deq = apply(enq, entries, pipe, flow) require(entries > 0, "Zero-entry queues don't guarantee Irrevocability") - val irr = Wire(new IrrevocableIO(deq.bits)) + val irr = Wire(new IrrevocableIO(chiselTypeOf(deq.bits))) irr.bits := deq.bits irr.valid := deq.valid deq.ready := irr.ready |