diff options
| author | Schuyler Eldridge | 2020-06-23 23:52:55 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-24 03:52:55 +0000 |
| commit | a1edc8f4cd525c8475e847ff7ddd9cb8fc1d3c51 (patch) | |
| tree | 39756f1e7b4359772643b349900e0c06d9aa6c2a /src/main/scala/chisel3 | |
| parent | 64dcd55c1c0b03f8bb9b72cd687fa3b2f416c631 (diff) | |
Add missing finishWrapper call in TesterDriver (#1496)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/testers/TesterDriver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index 2724da16..03fb1899 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -50,7 +50,7 @@ object TesterDriver extends BackendCompilationUtilities { Dependency[Emitter], Dependency[Convert])) - val annotationsx = pm.transform(ChiselGeneratorAnnotation(t) +: annotations) + val annotationsx = pm.transform(ChiselGeneratorAnnotation(finishWrapper(t)) +: annotations) val target: String = annotationsx.collectFirst { case FirrtlCircuitAnnotation(cir) => cir.main }.get val path = annotationsx.collectFirst { case TargetDirAnnotation(dir) => dir }.map(new File(_)).get |