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path: root/src/main/scala/chisel3/Driver.scala
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2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2021-11-29Deprecate chisel3.BackendCompilationUtilities (#2257)Jack Koenig
Also remove as many deprecated APIs as possible by inlining implementations of old deprecated/removed code from firrtl
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
It shouldn't be removed until we also remove the underlying chisel3.Driver.
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
* Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Deprecate Driver Execution classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-24Deprecate Driver methods in favor of ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Migrate to Dependency WrapperSchuyler Eldridge
This changes Phase dependency specification to use the new Dependency wrapper. Previously, dependencies were specified as classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-27Move stack trimming from Driver to ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
Migrate Driver to use a PhaseManager to internally resolve Phase ordering. This requires the use of an identity node to adequately describe the necessary prerequisite/dependents. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
This converts the original chisel3.Driver to use chisel3.stage.ChiselStage. This is implemented in the following way: 1. ExecutionOptions are converted to an AnnotationSeq 2. The AnnotationSeq is preprocessed using phases contained in the Chisel DriverCompatibility objects. One of these *disables* the execution of FirrtlStage by ChiselStage. 3. ChiselStage runs on the preprocessed AnnotationSeq 4. The input ExecutionOptionsManager is mutated based on the output of ChiselStage. 5. The FIRRTL stage is re-enabled if it's supposed to run and selected FIRRTL DriverCompatibility phases run. 6. FirrtlStage runs 7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult This modifies the original DriverSpec to make it more verbose with the addition of info statements. The functionality of the DriverSpec is unmodified. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`. This has been fixed in scalac 2.12.8 but projects using 2.11 in their cross-build need the `Predef.augmentString` patch. [Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
2018-11-26Trim Stack Trace (#931)Albert Chen
- Trim stack trace to show better, reduced information to the user - Add --full-stacktrace to FIRRTL option to show full stack trace
2018-09-28Add dumpAnnotations method to DriverSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-20Documentation tweaksedwardcwang
2018-07-02Direct to FIRRTL (#829)Jack Koenig
Provide direct conversion from ChiselIR to FIRRTL. Provide Driver support for dumping ProtoBuf.
2018-02-28Refactor Annotations (#767)Jack Koenig
* Generalize ChiselAnnotation This allows us to delay creation of Annotations till elaboration is complete. Also update all annotation-related code. * Add RunFirrtlTransform Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old ChiselAnnotation (now called ChiselLegacyAnnotation) * Use unique test directories in ChiselRunners.compile
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
This corrects the documented example for chisel3.Driver to mixin traits and not the related case classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
* Added API to get Verilog from Chisel * Removed second emitVerilog implementation, added scaladoc
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
Also make transform instantiation deterministic
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
Fixing a bug in passing down execution options to firrtl
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
Pass transforms along with Annotations when calling firrtl compiler This introduces new requirement that firrtl.Transform subclasses (that are associated with an annotation) do not have parameters in their default constructor Add new test for NoDedup annotation that shows how to annotate a module instance
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
* Support for creating chisel annotations that are consumed by firrtl Update annotation serialization in Driver Add DiamondAnnotation Spec that illustrates how to do simple annotations frontEnd must have dependency on firrtl Add annotation method to Module Circuit has extra optional parameter that is Seq of Annotations In Builder add annotation buffer to DynamicContext to store annotations created in modules Added explicit types on naming api methods to avoid type confusion Because some names are not available until elaboration create intermediate ChiselAnnotation that gets turned into a firrtl Annotation after elaboration In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though intermediate file .fir and .anno files are still created for inspection and/or later use * Somehow missed ChiselAnnotation * fixes for Jack's review of PR
2016-11-18Change Verilator invocation to use O1jackkoenig
Workaround for: http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
2016-11-17Eliminate some doc warningsducky
2016-10-19Change verilogToCpp to use O0jackkoenig
This causes Verilator tests to compile faster and use less memory
2016-10-14Implement a standardized execution scheme for chiselchick
Provide support for chisel options Provide support for firrtl options when called as part of chisel compile provide command line support the above options via scopt provide and execution result class that can be used when chisel3 is part of some externally controlled toolchain
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-10-06Merge branch 'master' into buildinfoJim Lawson
2016-10-06Update Driver: Check the simulation exit code #281Jim Lawson
Merge with master and support checking for failure with an explicit assertion message.
2016-10-05Print Chisel version when Driver object is created.Jim Lawson
2016-10-05Add sbt-buildinfo support.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Allow compileOptions as optional arguments to elaborate() and emit().Jim Lawson
2016-08-30Correct parameter name (topModule) in ScalaDoc.Jim Lawson
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