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| author | Jim Lawson | 2016-08-30 16:13:41 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-30 16:13:41 -0700 |
| commit | 19b7f92504dadce9226126751e25d8abbe17fcc3 (patch) | |
| tree | be8a8c0b92c567c4ec94b7c5a08e223eca6fa969 /src/main/scala/chisel3/Driver.scala | |
| parent | 8002f7ac6731b1da5e0d8e7b1536995a23878037 (diff) | |
| parent | 0c34480c5049c000e03b7b1a174e4bd6cca682cb (diff) | |
Merge branch 'master' into gsdt
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 8efb529d..f9f79f35 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -112,6 +112,8 @@ object Driver extends BackendCompilationUtilities { def emit[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): String = Emitter.emit(elaborate(gen, moduleCompileOptions)) + def emit[T <: Module](ir: Circuit): String = Emitter.emit(ir) + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { val f = optName.getOrElse(new File(ir.name + ".fir")) val w = new FileWriter(f) |