diff options
| author | Schuyler Eldridge | 2019-08-14 17:02:23 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-08-27 19:28:04 -0400 |
| commit | b48aba37ee6c422177359e6561e2694d8aaa4138 (patch) | |
| tree | 131f0b98d09dad3aea8ee9c69722c8d9216e3305 /src/main/scala/chisel3/Driver.scala | |
| parent | b7d1b325f56b2d1fadf0702efb8597a7d1ff9dff (diff) | |
Move stack trimming from Driver to ChiselStage
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index a78cc92f..158ba65a 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -6,7 +6,7 @@ import chisel3.internal.ErrorLog import chisel3.experimental.RawModule import internal.firrtl._ import firrtl._ -import firrtl.options.{Phase, PhaseManager} +import firrtl.options.{Phase, PhaseManager, StageError} import firrtl.options.phases.DeletedWrapper import firrtl.options.Viewer.view import firrtl.annotations.JsonProtocol @@ -226,16 +226,10 @@ object Driver extends BackendCompilationUtilities { val annosx = try { phases.foldLeft(annos)( (a, p) => p.transform(a) ) } catch { - case ce: ChiselException => - val stackTrace = if (!optionsManager.chiselOptions.printFullStackTrace) { - ce.chiselStackTrace - } else { - val sw = new StringWriter - ce.printStackTrace(new PrintWriter(sw)) - sw.toString - } - Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex line.size.limit - annos + /* ChiselStage and FirrtlStage can throw StageError. Since Driver is not a StageMain, it cannot catch these. While + * Driver is deprecated and removed in 3.2.1+, the Driver catches all errors. + */ + case e: StageError => annos } view[ChiselExecutionResult](annosx) |
