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authorJim Lawson2016-09-01 10:21:57 -0700
committerJim Lawson2016-09-01 13:08:44 -0700
commit4b88a5dd45337fa88178fe17324eef3661daf1b3 (patch)
tree225f34b9f0093b0f59bb66edacbb4cc2341a6d0b /src/main/scala/chisel3/Driver.scala
parent4e7e1c2b30bfa06f167b04aae4ef6944794323a9 (diff)
Move connection implicits from Module constructor to connection methods.
Eliminate builder compileOptions.
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
-rw-r--r--src/main/scala/chisel3/Driver.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f9f79f35..5e0a3a0f 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -108,9 +108,9 @@ object Driver extends BackendCompilationUtilities {
* @param gen a function that creates a Module hierarchy
* @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
*/
- def elaborate[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): Circuit = Builder.build(Module(gen()), moduleCompileOptions)
+ def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
- def emit[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): String = Emitter.emit(elaborate(gen, moduleCompileOptions))
+ def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
def emit[T <: Module](ir: Circuit): String = Emitter.emit(ir)