Move connection implicits from Module constructor to connection methods.

Eliminate builder compileOptions.

4 files changed, 5 insertions, 2 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f9f79f35..5e0a3a0f 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -108,9 +108,9 @@ object Driver extends BackendCompilationUtilities {
     *  @param gen a function that creates a Module hierarchy
     *  @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
     */
-  def elaborate[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): Circuit = Builder.build(Module(gen()), moduleCompileOptions)
+  def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
 
-  def emit[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): String = Emitter.emit(elaborate(gen, moduleCompileOptions))
+  def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
 
   def emit[T <: Module](ir: Circuit): String = Emitter.emit(ir)
 
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 1c95190b..441f5c5b 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -3,6 +3,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.Strict.CompileOptions
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index a30c276f..7146af7e 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.Strict.CompileOptions
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 37c28b14..8a9c54a2 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.Strict.CompileOptions
 
 object RegNext {