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authorSchuyler Eldridge2019-12-09 21:27:32 -0500
committerSchuyler Eldridge2020-02-19 20:52:33 -0500
commit9f20d7d4e29c7a864d81f15607b65d2b887fc828 (patch)
treed6b8b05c834ac68fb3962b481279b0143ad77c16 /src/main/scala/chisel3/Driver.scala
parentaac6e175645960b65eace70d16d0e4df523e0327 (diff)
Migrate to Dependency Wrapper
This changes Phase dependency specification to use the new Dependency wrapper. Previously, dependencies were specified as classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
-rw-r--r--src/main/scala/chisel3/Driver.scala20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 1caccfc4..28ed49ed 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -5,7 +5,7 @@ package chisel3
import chisel3.internal.ErrorLog
import internal.firrtl._
import firrtl._
-import firrtl.options.{Phase, PhaseManager, StageError}
+import firrtl.options.{Dependency, Phase, PhaseManager, StageError}
import firrtl.options.phases.DeletedWrapper
import firrtl.options.Viewer.view
import firrtl.annotations.JsonProtocol
@@ -207,16 +207,16 @@ object Driver extends BackendCompilationUtilities {
optionsManager.commonOptions.toAnnotations
val targets =
- Seq( classOf[DriverCompatibility.AddImplicitOutputFile],
- classOf[DriverCompatibility.AddImplicitOutputAnnotationFile],
- classOf[DriverCompatibility.DisableFirrtlStage],
- classOf[ChiselStage],
- classOf[DriverCompatibility.MutateOptionsManager],
- classOf[DriverCompatibility.ReEnableFirrtlStage],
- classOf[DriverCompatibility.FirrtlPreprocessing],
- classOf[chisel3.stage.phases.MaybeFirrtlStage] )
+ Seq( Dependency[DriverCompatibility.AddImplicitOutputFile],
+ Dependency[DriverCompatibility.AddImplicitOutputAnnotationFile],
+ Dependency[DriverCompatibility.DisableFirrtlStage],
+ Dependency[ChiselStage],
+ Dependency[DriverCompatibility.MutateOptionsManager],
+ Dependency[DriverCompatibility.ReEnableFirrtlStage],
+ Dependency[DriverCompatibility.FirrtlPreprocessing],
+ Dependency[chisel3.stage.phases.MaybeFirrtlStage] )
val currentState =
- Seq( classOf[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile] )
+ Seq( Dependency[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile] )
val phases: Seq[Phase] = new PhaseManager(targets, currentState) {
override val wrappers = Seq( DeletedWrapper(_: Phase) )