Move blackbox verilog implementations within reach of verilator (#453)

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command

1 files changed, 16 insertions, 3 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f4a7d0e5..f9f6dabe 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -113,10 +113,23 @@ trait BackendCompilationUtilities {
       vSources: Seq[File],
       cppHarness: File
                   ): ProcessBuilder = {
-    val command = Seq("verilator",
-      "--cc", s"$dutFile.v") ++
+    val blackBoxVerilogList = {
+      val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.FileListName)
+      if(list_file.exists()) {
+        Seq("-f", list_file.getAbsolutePath)
+      }
+      else {
+        Seq.empty[String]
+      }
+    }
+    val command = Seq(
+        "verilator",
+        "--cc", s"$dutFile.v"
+      ) ++
+      blackBoxVerilogList ++
       vSources.map(file => Seq("-v", file.toString)).flatten ++
-      Seq("--assert",
+      Seq(
+        "--assert",
         "-Wno-fatal",
         "-Wno-WIDTH",
         "-Wno-STMTDLY",