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path: root/src/main/scala/chisel3/Driver.scala
AgeCommit message (Expand)Author
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-11-18Change Verilator invocation to use O1jackkoenig
2016-11-17Eliminate some doc warningsducky
2016-10-19Change verilogToCpp to use O0jackkoenig
2016-10-14Implement a standardized execution scheme for chiselchick
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-10-06Merge branch 'master' into buildinfoJim Lawson
2016-10-06Update Driver: Check the simulation exit code #281Jim Lawson
2016-10-05Print Chisel version when Driver object is created.Jim Lawson
2016-10-05Add sbt-buildinfo support.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Allow compileOptions as optional arguments to elaborate() and emit().Jim Lawson
2016-08-30Correct parameter name (topModule) in ScalaDoc.Jim Lawson
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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