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AgeCommit message (Expand)Author
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
2017-02-28Fix minor typo in readme (#537)Siddhanathan Shanmugam
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Record: allow elements to start with a digitWesley W. Terpstra
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
2017-02-24Test that large Vecs can have widths inferredjackkoenig
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-23Fend off future bug - replace FixedPoint ":=" with "connect". (#516)Jim Lawson
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
2017-02-21Use chisel3 in libraryDependencies example. (#520)Jim Lawson
2017-02-17Builderreflectionfix (#515)Angie Wang
2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
2017-02-08Bump sbt version.Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
2017-02-03Fix potential NPE if we try to evaluate isMissingIOWrapper() inside IO(). (#479)Jim Lawson
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31fix buildInfoPackage name (and comment)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-30Add shift register with reset (#439)Stevo
2017-01-27Add pointer to ScalaDoc. (#397)Jim Lawson
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-27Add basic Chisel2 compatibility sanity checks. (#340)Jim Lawson
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