Use test_run_dir for more tests. (#534)

* Use test_run_dir for more tests.

* Use official option and DRY.

Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.

5 files changed, 59 insertions, 15 deletions

diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
index 3f255083..f792c56f 100644
--- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
+++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
@@ -142,7 +142,7 @@ class AnnotatingDiamondSpec extends FreeSpec with Matchers {
       |annotations are not resolved at after circuit elaboration,
       |that happens only after emit has been called on circuit""".stripMargin in {
 
-      Driver.execute(Array.empty[String], () => new TopOfDiamond) match {
+      Driver.execute(Array("--target-dir", "test_run_dir"), () => new TopOfDiamond) match {
         case ChiselExecutionSuccess(Some(circuit), emitted, _) =>
           val annos = circuit.annotations
           annos.length should be (10)
diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala
index 7c7c0583..93167f69 100644
--- a/src/test/scala/chiselTests/AnnotationNoDedup.scala
+++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala
@@ -50,7 +50,7 @@ class UsesMuchUsedModule(addAnnos: Boolean) extends Module with NoDedupAnnotator
 class AnnotationNoDedup extends FreeSpec with Matchers {
   "Firrtl provides transform that reduces identical modules to a single instance" - {
     "Annotations can be added which will defeat this deduplication for specific modules instances" in {
-      Driver.execute(Array("-X", "low"), () => new UsesMuchUsedModule(addAnnos = true)) match {
+      Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new UsesMuchUsedModule(addAnnos = true)) match {
         case ChiselExecutionSuccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
           val lowFirrtl = firrtlResult.emitted
 
@@ -63,7 +63,7 @@ class AnnotationNoDedup extends FreeSpec with Matchers {
       }
     }
     "Turning off these nnotations dedup all the occurrences" in {
-      Driver.execute(Array("-X", "low"), () => new UsesMuchUsedModule(addAnnos = false)) match {
+      Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new UsesMuchUsedModule(addAnnos = false)) match {
         case ChiselExecutionSuccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
           val lowFirrtl = firrtlResult.emitted
 
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index 9e817486..11d59fe9 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -65,11 +65,12 @@ class UsesBlackBoxMinusViaResource extends Module {
 }
 
 class BlackBoxImplSpec extends FreeSpec with Matchers {
+  val targetDir = "test_run_dir"
   "BlackBox can have verilator source implementation" - {
     "Implementations can be contained in-line" in {
-      Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match {
+      Driver.execute(Array("-X", "verilog", "--target-dir", targetDir), () => new UsesBlackBoxAddViaInline) match {
         case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val verilogOutput = new File("./BlackBoxAdd.v")
+          val verilogOutput = new File(targetDir, "BlackBoxAdd.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
           Succeeded
@@ -78,9 +79,9 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
       }
     }
     "Implementations can be contained in resource files" in {
-      Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match {
+      Driver.execute(Array("-X", "low", "--target-dir", targetDir), () => new UsesBlackBoxMinusViaResource) match {
         case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val verilogOutput = new File("./BlackBoxTest.v")
+          val verilogOutput = new File(targetDir, "BlackBoxTest.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
           Succeeded
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 55d58d77..584f134c 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -9,6 +9,7 @@ import org.scalacheck._
 import chisel3._
 import chisel3.testers._
 import firrtl.{
+  CommonOptions,
   ExecutionOptionsManager,
   HasFirrtlOptions,
   FirrtlExecutionSuccess,
@@ -35,10 +36,17 @@ trait ChiselRunners extends Assertions {
     */
   def generateFirrtl(t: => Module): String = Driver.emit(() => t)
 
-  /** Compiles a Chisel Module to Verilog */
+  /** Compiles a Chisel Module to Verilog
+    * NOTE: This uses the "test_run_dir" as the default directory for generated code.
+    * @param t the generator for the module
+    * @return the Verilog code as a string.
+    */
   def compile(t: => Module): String = {
     val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions
-                                                         with HasChiselExecutionOptions
+                                                         with HasChiselExecutionOptions {
+      commonOptions = CommonOptions(targetDirName = "test_run_dir")
+    }
+
     Driver.execute(manager, () => t) match {
       case ChiselExecutionSuccess(_, _, Some(firrtlExecRes)) =>
         firrtlExecRes match {
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index b68b2810..796668e3 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -2,9 +2,12 @@
 
 package chiselTests
 
-import chisel3._
+import java.io.File
 
-import org.scalatest.{Matchers, FreeSpec}
+import chisel3._
+import firrtl.FirrtlExecutionSuccess
+import org.scalacheck.Test.Failed
+import org.scalatest.{FreeSpec, Matchers, Succeeded}
 
 class DummyModule extends Module {
   val io = IO(new Bundle {
@@ -17,17 +20,49 @@ class DummyModule extends Module {
 class DriverSpec extends FreeSpec with Matchers {
   "Driver's execute methods are used to run chisel and firrtl" - {
     "options can be picked up from comand line with no args" in {
-      Driver.execute(Array.empty[String], () => new DummyModule)
+      // NOTE: Since we don't provide any arguments (notably, "--target-dir"),
+      //  the generated files will be created in the current directory.
+      val  targetDir = "."
+      Driver.execute(Array.empty[String], () => new DummyModule) match {
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+          val exts = List("anno", "fir", "v")
+          for (ext <- exts) {
+            val dummyOutput = new File(targetDir, "DummyModule" + "." + ext)
+            dummyOutput.exists() should be(true)
+            dummyOutput.delete()
+          }
+          Succeeded
+        case _ =>
+          Failed
+      }
     }
+
     "options can be picked up from comand line setting top name" in {
-      Driver.execute(Array("-tn", "dm", "-td", "local-build"), () => new DummyModule)
+      val  targetDir = "local-build"
+      Driver.execute(Array("-tn", "dm", "-td", targetDir), () => new DummyModule) match {
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+          val exts = List("anno", "fir", "v")
+          for (ext <- exts) {
+            val dummyOutput = new File(targetDir, "dm" + "." + ext)
+            dummyOutput.exists() should be(true)
+            dummyOutput.delete()
+          }
+          Succeeded
+        case _ =>
+          Failed
+      }
+
     }
     "execute returns a chisel execution result" in {
-      val args = Array("--compiler", "low")
-      val result = Driver.execute(Array.empty[String], () => new DummyModule)
+      val targetDir = "test_run_dir"
+      val args = Array("--compiler", "low", "--target-dir", targetDir)
+      val result = Driver.execute(args, () => new DummyModule)
       result shouldBe a[ChiselExecutionSuccess]
       val successResult = result.asInstanceOf[ChiselExecutionSuccess]
       successResult.emitted should include ("circuit DummyModule")
+      val dummyOutput = new File(targetDir, "DummyModule.lo.fir")
+      dummyOutput.exists() should be(true)
+      dummyOutput.delete()
     }
   }
 }