diff options
| author | Donggyu Kim | 2016-08-15 18:03:12 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-08-21 22:28:03 -0700 |
| commit | 2d01fdf6f26f480cb7ed19c1365f181ea717ddc2 (patch) | |
| tree | 75eecb6157ada9471d17bc9fb082d091b969da34 /src/main/scala/chisel3/Driver.scala | |
| parent | 0744b3e5f9c0648878b97d3375cd7d88e2d0ee08 (diff) | |
provides signal name methods for firrtl annotation and chisel testers
* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 0979314f..5aeeef99 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -112,6 +112,8 @@ object Driver extends BackendCompilationUtilities { def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) + def emit[T <: Module](ir: Circuit): String = Emitter.emit(ir) + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { val f = optName.getOrElse(new File(ir.name + ".fir")) val w = new FileWriter(f) |