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path: root/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
AgeCommit message (Expand)Author
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2016-11-21Break out deprecated literal constructors, refactor all the things!ducky
2016-10-23create SeqMems' read ports inside when statementDonggyu Kim
2016-10-05Use modulo addressing for dynamic Vec/Mem accessesAndrew Waterman
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-09Convert to NotStrict for internal connection checks.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson