diff options
| author | Jim Lawson | 2016-07-20 14:49:35 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 14:49:35 -0700 |
| commit | 2dce378deda1cc33833eb378c89a1c5415817bae (patch) | |
| tree | e3bc5361030d63e017d065491e9e7e4cf788fe3c /chiselFrontend/src/main/scala/chisel3/core/Mem.scala | |
| parent | 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff) | |
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Mem.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a9854362..a4e6bee3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -36,7 +36,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi /** Creates a read accessor into the memory with static addressing. See the * class documentation of the memory for more detailed information. */ - def apply(idx: Int): T = apply(UInt(idx)) + def apply(idx: Int): T = apply(UInt.Lit(idx)) /** Creates a read/write accessor into the memory with dynamic addressing. * See the class documentation of the memory for more detailed information. |
