diff options
36 files changed, 195 insertions, 173 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 666d8283..a80dfec8 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -241,7 +241,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { /** Helper function that appends an index (literal value) to each element, * useful for hardware generators which output an index. */ - private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i)) + private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt.Lit(i)) /** Outputs the index of the first element for which p outputs true. */ diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index e8aae578..3580b5f3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -270,9 +270,9 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) def do_toBool(implicit sourceInfo: SourceInfo): Bool = { width match { - case KnownWidth(1) => this(0) - case _ => throwException(s"can't covert UInt<$width> to Bool") - } + case KnownWidth(1) => this(0) + case _ => throwException(s"can't covert UInt<$width> to Bool") + } } /** Returns this wire concatenated with `other`, where this wire forms the @@ -407,8 +407,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) final def unary_- (): UInt = macro SourceInfoTransform.noArg final def unary_-% (): UInt = macro SourceInfoTransform.noArg - def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this - def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this + def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt.Lit(0) - this + def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt.Lit(0) -% this override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that @@ -456,8 +456,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) final def andR(): Bool = macro SourceInfoTransform.noArg final def xorR(): Bool = macro SourceInfoTransform.noArg - def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0) - def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0) + def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt.Lit(0) + def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt.Lit(0) def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp) override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that) @@ -523,14 +523,25 @@ private[core] sealed trait UIntFactory { /** Create a UInt port with specified width. */ def apply(width: Width): UInt = new UInt(width) /** Create a UInt with a specified width - compatibility with Chisel2. */ + def width(width: Int): UInt = apply(Width(width)) + /** Create a UInt port with specified width. */ + def width(width: Width): UInt = new UInt(width) + /** Create a UInt with a specified width - compatibility with Chisel2. */ def apply(dummy: Direction, width: Int): UInt = apply(Width(width)) /** Create a UInt literal with fixed width. */ - def apply(value: BigInt, width: Int): UInt = apply(value, Width(width)) + def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width)) /** Create a UInt literal with inferred width. */ - def apply(n: String): UInt = apply(parse(n), parsedWidth(n)) - /** Create a UInt literal with fixed width. */ + def apply(n: String): UInt = Lit(n) /** Create a UInt literal with specified width. */ - def apply(value: BigInt, width: Width): UInt = { + def apply(value: BigInt, width: Width): UInt = Lit(value, width) + def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width)) + /** Create a UInt literal with inferred width. */ + def Lit(value: BigInt): UInt = Lit(value, Width()) + def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n)) + /** Create a UInt literal with fixed width. */ + def Lit(n: String, width: Int): UInt = Lit(parse(n), width) + /** Create a UInt literal with specified width. */ + def Lit(value: BigInt, width: Width): UInt = { val lit = ULit(value, width) val result = new UInt(lit.width, Some(lit)) // Bind result to being an Literal @@ -575,8 +586,8 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None) final def unary_- (): SInt = macro SourceInfoTransform.noArg final def unary_-% (): SInt = macro SourceInfoTransform.noArg - def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this - def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this + def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt.Lit(0) - this + def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt.Lit(0) -% this /** add (default - no growth) operator */ override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt = @@ -643,7 +654,7 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None) final def abs(): UInt = macro SourceInfoTransform.noArg - def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt) + def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt.Lit(0), (-this).asUInt, this.asUInt) override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt = binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that) @@ -669,14 +680,24 @@ object SInt { def apply(width: Int): SInt = apply(Width(width)) /** Create an SInt type with specified width. */ def apply(width: Width): SInt = new SInt(width) + /** Create a SInt type or port with fixed width. */ + def width(width: Int): SInt = apply(Width(width)) + /** Create an SInt type with specified width. */ + def width(width: Width): SInt = new SInt(width) /** Create an SInt literal with inferred width. */ - def apply(value: BigInt): SInt = apply(value, Width()) + def apply(value: BigInt): SInt = Lit(value) /** Create an SInt literal with fixed width. */ - def apply(value: BigInt, width: Int): SInt = apply(value, Width(width)) + def apply(value: BigInt, width: Int): SInt = Lit(value, width) /** Create an SInt literal with specified width. */ - def apply(value: BigInt, width: Width): SInt = { + def apply(value: BigInt, width: Width): SInt = Lit(value, width) + + def Lit(value: BigInt): SInt = Lit(value, Width()) + def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width)) + /** Create an SInt literal with specified width. */ + def Lit(value: BigInt, width: Width): SInt = { + val lit = SLit(value, width) val result = new SInt(lit.width, Some(lit)) // Bind result to being an Literal @@ -737,7 +758,8 @@ object Bool { /** Creates Bool literal. */ - def apply(x: Boolean): Bool = { + def apply(x: Boolean): Bool = Lit(x) + def Lit(x: Boolean): Bool = { val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1)))) // Bind result to being an Literal result.binding = LitBinding() @@ -754,7 +776,7 @@ object Mux { * @param alt the value chosen when `cond` is false * @example * {{{ - * val muxOut = Mux(data_in === UInt(3), UInt(3, 4), UInt(0, 4)) + * val muxOut = Mux(data_in === UInt.Lit(3), UInt(3, 4), UInt(0, 4)) * }}} */ def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T] diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a9854362..a4e6bee3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -36,7 +36,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi /** Creates a read accessor into the memory with static addressing. See the * class documentation of the memory for more detailed information. */ - def apply(idx: Int): T = apply(UInt(idx)) + def apply(idx: Int): T = apply(UInt.Lit(idx)) /** Creates a read/write accessor into the memory with dynamic addressing. * See the class documentation of the memory for more detailed information. diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 91cb9e89..c1ec6b90 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -25,11 +25,11 @@ private[chisel3] object SeqUtils { def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = { if (in.size == 0) { - UInt(0) + UInt.Lit(0) } else if (in.size == 1) { in.head } else { - count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size))) + count(in.slice(0, in.size/2)) + (UInt.Lit(0) ## count(in.slice(in.size/2, in.size))) } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala index 196e7903..7049eb82 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/When.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala @@ -18,9 +18,9 @@ object when { // scalastyle:ignore object.name * * @example * {{{ - * when ( myData === UInt(3) ) { + * when ( myData === UInt.Lit(3) ) { * // Some logic to run when myData equals 3. - * } .elsewhen ( myData === UInt(1) ) { + * } .elsewhen ( myData === UInt.Lit(1) ) { * // Some logic to run when myData equals 1. * } .otherwise { * // Some logic to run when myData is neither 3 nor 1. diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 86fce6a2..e43434c0 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -95,7 +95,7 @@ package object chisel3 { def asSInt(width: Int) = SInt(x, width) } implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) + def U: UInt = UInt.Lit(x) } implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { def B: Bool = Bool(x) diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index a5397682..44cc88b6 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -36,7 +36,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo if (count > 1) { val lockCount = Counter(count) val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt(0) + val locked = lockCount.value =/= UInt.Lit(0) val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) when (io.out.firing && wantsLock) { @@ -46,7 +46,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo when (locked) { io.chosen := lockIdx } for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready } else { for ((in, g) <- io.in zip grant) in.ready := g && io.out.ready @@ -66,9 +66,9 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt(i) } + when (validMask(i)) { choice := UInt.Lit(i) } } class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) @@ -77,7 +77,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } } /** Hardware module that is used to sequence n producers into 1 consumer. @@ -107,7 +107,7 @@ class Arbiter[T <: Data](gen: T, n: Int) extends Module { io.out.bits := io.in(n-1).bits for (i <- n-2 to 0 by -1) { when (io.in(i).valid) { - io.chosen := UInt(i) + io.chosen := UInt.Lit(i) io.out.bits := io.in(i).bits } } diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index 1174c71c..5e93b009 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -11,12 +11,12 @@ import chisel3._ * An alternative interpretation is it computes the minimum number of bits needed to represent x * @example * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ + * @note Truncation is used so Log2(UInt.Lit(12412)) = 13*/ object Log2 { /** Compute the Log2 on the least significant n bits of x */ def apply(x: Bits, width: Int): UInt = { if (width < 2) { - UInt(0) + UInt.Lit(0) } else if (width == 2) { x(1) } else { diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index 40615769..05d8fba8 100644 --- a/src/main/scala/chisel3/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -10,17 +10,17 @@ import chisel3._ */ class Counter(val n: Int) { require(n >= 0) - val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) + val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0) /** Increment the counter, returning whether the counter currently is at the * maximum and will wrap. The incremented value is registered and will be * visible on the next cycle. */ def inc(): Bool = { if (n > 1) { - val wrap = value === UInt(n-1) - value := value + UInt(1) + val wrap = value === UInt.Lit(n-1) + value := value + UInt.Lit(1) if (!isPow2(n)) { - when (wrap) { value := UInt(0) } + when (wrap) { value := UInt.Lit(0) } } wrap } else { @@ -33,7 +33,7 @@ class Counter(val n: Int) { * Example Usage: * {{{ val countOn = Bool(true) // increment counter every clock cycle * val myCounter = Counter(countOn, n) - * when ( myCounter.value === UInt(3) ) { ... } }}}*/ + * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/ object Counter { def apply(n: Int): Counter = new Counter(n) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index fb1ee6b9..5958c744 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -153,9 +153,9 @@ extends Module(override_reset=override_reset) { } else { io.count := Mux(ptr_match, Mux(maybe_full, - UInt(entries), UInt(0)), + UInt.Lit(entries), UInt.Lit(0)), Mux(deq_ptr.value > enq_ptr.value, - UInt(entries) + ptr_diff, ptr_diff)) + UInt.Lit(entries) + ptr_diff, ptr_diff)) } } diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index 4d816a19..3a9089c5 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -5,6 +5,6 @@ package chisel3.util import chisel3._ object ImplicitConversions { - implicit def intToUInt(x: Int): UInt = UInt(x) + implicit def intToUInt(x: Int): UInt = UInt.Lit(x) implicit def booleanToBool(x: Boolean): Bool = Bool(x) } diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala index 820c72d6..8a5caf44 100644 --- a/src/main/scala/chisel3/util/OneHot.scala +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -41,9 +41,9 @@ object UIntToOH { def apply(in: UInt, width: Int = -1): UInt = if (width == -1) { - UInt(1) << in + UInt.Lit(1) << in } else { - (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0) } } diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index efc2e1e7..bf3c8092 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester { class PipelinedResetModule extends Module { val io = IO(new Bundle { }) - val a = Reg(init = UInt(0xbeef)) - val b = Reg(init = UInt(0xbeef)) + val a = Reg(init = UInt.Lit(0xbeef)) + val b = Reg(init = UInt.Lit(0xbeef)) assert(a === b) } diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index c1154883..9b43f0ef 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester { val blackBoxPos = Module(new BlackBoxInverter) val blackBoxNeg = Module(new BlackBoxInverter) - blackBoxPos.io.in := UInt(1) - blackBoxNeg.io.in := UInt(0) + blackBoxPos.io.in := UInt.Lit(1) + blackBoxNeg.io.in := UInt.Lit(0) - assert(blackBoxNeg.io.out === UInt(1)) - assert(blackBoxPos.io.out === UInt(0)) + assert(blackBoxNeg.io.out === UInt.Lit(1)) + assert(blackBoxPos.io.out === UInt.Lit(0)) stop() } @@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester { val blackBoxPassPos = Module(new BlackBoxPassthrough) val blackBoxPassNeg = Module(new BlackBoxPassthrough) - blackBoxInvPos.io.in := UInt(1) - blackBoxInvNeg.io.in := UInt(0) - blackBoxPassPos.io.in := UInt(1) - blackBoxPassNeg.io.in := UInt(0) + blackBoxInvPos.io.in := UInt.Lit(1) + blackBoxInvNeg.io.in := UInt.Lit(0) + blackBoxPassPos.io.in := UInt.Lit(1) + blackBoxPassNeg.io.in := UInt.Lit(0) - assert(blackBoxInvNeg.io.out === UInt(1)) - assert(blackBoxInvPos.io.out === UInt(0)) - assert(blackBoxPassNeg.io.out === UInt(0)) - assert(blackBoxPassPos.io.out === UInt(1)) + assert(blackBoxInvNeg.io.out === UInt.Lit(1)) + assert(blackBoxInvPos.io.out === UInt.Lit(0)) + assert(blackBoxPassNeg.io.out === UInt.Lit(0)) + assert(blackBoxPassPos.io.out === UInt.Lit(1)) stop() } @@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester { blackBox.io.in := impetus model := impetus - when(cycles > UInt(0)) { + when(cycles > UInt.Lit(0)) { assert(blackBox.io.out === model) } when(end) { stop() } @@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester { val (cycles, end) = Counter(Bool(true), 4) - assert(blackBoxOne.io.out === UInt(1)) - assert(blackBoxFour.io.out === UInt(4)) + assert(blackBoxOne.io.out === UInt.Lit(1)) + assert(blackBoxFour.io.out === UInt.Lit(4)) when(end) { stop() } } diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 029407dd..2f6322b1 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module { class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester { val dut = Module(new BundleWire(n)) - dut.io.in.x := UInt(x) - dut.io.in.y := UInt(y) + dut.io.in.x := UInt.Lit(x) + dut.io.in.y := UInt.Lit(y) for (elt <- dut.io.outs) { - assert(elt.x === UInt(x)) - assert(elt.y === UInt(y)) + assert(elt.x === UInt.Lit(x)) + assert(elt.y === UInt.Lit(y)) } stop() } diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index e5d1fbea..638ef9b7 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module { io.out.re := tmp.re io.out.im := tmp.im } .otherwise { - io.out.re := UInt(0) - io.out.im := UInt(0) + io.out.re := UInt.Lit(0) + io.out.im := UInt.Lit(0) } } class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), enList.size) val dut = Module(new ComplexAssign(32)) - dut.io.in.re := UInt(re) - dut.io.in.im := UInt(im) + dut.io.in.re := UInt.Lit(re) + dut.io.in.im := UInt.Lit(im) dut.io.e := Vec(enList.map(Bool(_)))(cnt) - val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0)) - val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0)) + val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0)) + val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0)) assert(re_correct && im_correct) when(wrap) { stop() diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index 69d8a44a..af2fa550 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -12,20 +12,20 @@ import chisel3.util._ class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) when(Bool(true)) { cnt.inc() } - when(cnt.value === UInt(max-1)) { + when(cnt.value === UInt.Lit(max-1)) { stop() } } class EnableTester(seed: Int) extends BasicTester { - val ens = Reg(init = UInt(seed)) + val ens = Reg(init = UInt.Lit(seed)) ens := ens >> 1 val (cntEnVal, _) = Counter(ens(0), 32) val (_, done) = Counter(Bool(true), 33) when(done) { - assert(cntEnVal === UInt(popCount(seed))) + assert(cntEnVal === UInt.Lit(popCount(seed))) stop() } } @@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester { class WrapTester(max: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), max) when(wrap) { - assert(cnt === UInt(max - 1)) + assert(cnt === UInt.Lit(max - 1)) stop() } } diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index 4a872245..ee892fc5 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -12,7 +12,7 @@ import chisel3.util._ class Decoder(bitpats: List[String]) extends Module { val io = IO(new Bundle { - val inst = Input(UInt(32)) + val inst = Input(UInt.width(32)) val matched = Output(Bool()) }) io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_) @@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester { val dut = Module(new Decoder(bitpats)) dut.io.inst := Vec(insts.map(UInt(_)))(cnt) when(!dut.io.matched) { - assert(cnt === UInt(0)) + assert(cnt === UInt.Lit(0)) stop() } when(wrap) { diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 682103f7..e22e120b 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -9,17 +9,17 @@ import chisel3.testers.BasicTester class DirectionHaver extends Module { val io = IO(new Bundle { - val in = Input(UInt(32)) - val out = Output(UInt(32)) + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) }) } class GoodDirection extends DirectionHaver { - io.out := UInt(0) + io.out := UInt.Lit(0) } class BadDirection extends DirectionHaver { - io.in := UInt(0) + io.in := UInt.Lit(0) } class DirectionSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 26af944f..5f3e0dd1 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -6,9 +6,9 @@ import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = IO(new Bundle { - val in = Input(UInt(4)) + val in = Input(UInt.width(4)) val shift = Input(Bool()) - val out = Output(UInt(4)) + val out = Output(UInt.width(4)) }) val r0 = Reg(init = UInt(0, 4)) val r1 = Reg(init = UInt(0, 4)) diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 7c04ae00..d0d945b7 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -9,10 +9,10 @@ import org.scalatest.prop._ class GCD extends Module { val io = IO(new Bundle { - val a = Input(UInt(32)) - val b = Input(UInt(32)) + val a = Input(UInt.width(32)) + val b = Input(UInt.width(32)) val e = Input(Bool()) - val z = Output(UInt(32)) + val z = Output(UInt.width(32)) val v = Output(Bool()) }) val x = Reg(UInt(width = 32)) diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index 2d5e7f3e..b13b67e3 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -9,7 +9,7 @@ import chisel3.util._ class LFSR16 extends Module { val io = IO(new Bundle { val inc = Input(Bool()) - val out = Output(UInt(16)) + val out = Output(UInt.width(16)) }) val res = Reg(init = UInt(1, 16)) when (io.inc) { diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 770be326..e4063532 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -7,21 +7,21 @@ import chisel3.testers.BasicTester class MemorySearch extends Module { val io = IO(new Bundle { - val target = Input(UInt(4)) + val target = Input(UInt.width(4)) val en = Input(Bool()) val done = Output(Bool()) - val address = Output(UInt(3)) + val address = Output(UInt.width(3)) }) val vals = Array(0, 4, 15, 14, 2, 5, 13) val index = Reg(init = UInt(0, width = 3)) val elts = Vec(vals.map(UInt(_,4))) // val elts = Mem(UInt(width = 32), 8) TODO ???? val elt = elts(index) - val end = !io.en && ((elt === io.target) || (index === UInt(7))) + val end = !io.en && ((elt === io.target) || (index === UInt.Lit(7))) when (io.en) { - index := UInt(0) + index := UInt.Lit(0) } .elsewhen (!end) { - index := index +% UInt(1) + index := index +% UInt.Lit(1) } io.done := end io.address := index diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 857aeda3..59451a2b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -5,8 +5,8 @@ package chiselTests import chisel3._ class SimpleIO extends Bundle { - val in = Input(UInt(32)) - val out = Output(UInt(32)) + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) } class PlusOne extends Module { @@ -16,8 +16,8 @@ class PlusOne extends Module { class ModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Input(Vec(n, UInt(32))) - val outs = Output(Vec(n, UInt(32))) + val ins = Input(Vec(n, UInt.Lit(32))) + val outs = Output(Vec(n, UInt.Lit(32))) }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index b22b2820..16a29104 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -9,9 +9,9 @@ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { val io = IO(new Bundle { - val x = Input(UInt(w)) - val y = Input(UInt(w)) - val z = Output(UInt(2 * w)) + val x = Input(UInt.width(w)) + val y = Input(UInt.width(w)) + val z = Output(UInt.width(2 * w)) }) val tbl = Vec( for { @@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module { class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester { val dut = Module(new MulLookup(w)) - dut.io.x := UInt(x) - dut.io.y := UInt(y) - assert(dut.io.z === UInt(x * y)) + dut.io.x := UInt.Lit(x) + dut.io.y := UInt.Lit(y) + assert(dut.io.z === UInt.Lit(x * y)) stop() } diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 6c92e87b..42df6802 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -6,9 +6,9 @@ import chisel3._ class Padder extends Module { val io = IO(new Bundle { - val a = Input(UInt(4)) - val asp = Output(SInt(8)) - val aup = Output(UInt(8)) + val a = Input(UInt.width(4)) + val asp = Output(SInt.width(8)) + val aup = Output(UInt.width(8)) }) io.asp := io.a.asSInt io.aup := io.a.asUInt diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index c872fde4..92b6fee1 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -7,7 +7,7 @@ import chisel3._ import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { - val x = UInt(254) + val x = UInt.Lit(254) printf("x=%x", x) stop() } @@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester { } class MultiPrintfTester() extends BasicTester { - val x = UInt(254) - val y = UInt(255) + val x = UInt.Lit(254) + val y = UInt.Lit(255) printf("x=%x y=%x", x, y) stop() } diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 0caf6315..5d4bd18d 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) + val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index c110d37e..156e5df2 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -8,7 +8,7 @@ import chisel3.util._ class Risc extends Module { val io = IO(new Bundle { val isWr = Input(Bool()) - val wrAddr = Input(UInt(8)) + val wrAddr = Input(UInt.width(8)) val wrData = Input(Bits(32)) val boot = Input(Bool()) val valid = Output(Bool()) @@ -38,7 +38,7 @@ class Risc extends Module { when (io.isWr) { code(io.wrAddr) := io.wrData } .elsewhen (io.boot) { - pc := UInt(0) + pc := UInt.Lit(0) } .otherwise { switch(op) { is(add_op) { rc := ra +% rb } diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index a98edf9b..d827c096 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -7,22 +7,22 @@ import chisel3.testers.BasicTester class SIntOps extends Module { val io = IO(new Bundle { - val a = Input(SInt(16)) - val b = Input(SInt(16)) - val addout = Output(SInt(16)) - val subout = Output(SInt(16)) - val timesout = Output(SInt(16)) - val divout = Output(SInt(16)) - val modout = Output(SInt(16)) - val lshiftout = Output(SInt(16)) - val rshiftout = Output(SInt(16)) + val a = Input(SInt.width(16)) + val b = Input(SInt.width(16)) + val addout = Output(SInt.width(16)) + val subout = Output(SInt.width(16)) + val timesout = Output(SInt.width(16)) + val divout = Output(SInt.width(16)) + val modout = Output(SInt.width(16)) + val lshiftout = Output(SInt.width(16)) + val rshiftout = Output(SInt.width(16)) val lessout = Output(Bool()) val greatout = Output(Bool()) val eqout = Output(Bool()) val noteqout = Output(Bool()) val lesseqout = Output(Bool()) val greateqout = Output(Bool()) - val negout = Output(SInt(16)) + val negout = Output(SInt.width(16)) }) val a = io.a @@ -32,9 +32,9 @@ class SIntOps extends Module { io.subout := a -% b // TODO: //io.timesout := (a * b)(15, 0) - //io.divout := a / Mux(b === SInt(0), SInt(1), b) + //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b) //io.divout := (a / b)(15, 0) - //io.modout := SInt(0) + //io.modout := SInt.Lit(0) //io.lshiftout := (a << 12)(15, 0) // (a << ub(3, 0))(15, 0).toSInt io.rshiftout := (a >> 8) // (a >> ub).toSInt io.lessout := a < b @@ -44,7 +44,7 @@ class SIntOps extends Module { io.lesseqout := a <= b io.greateqout := a >= b // io.negout := -a(15, 0).toSInt - io.negout := (SInt(0) -% a) + io.negout := (SInt.Lit(0) -% a) } /* diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 683c5224..440228c9 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -12,8 +12,8 @@ class ChiselStack(val depth: Int) extends Module { val push = Input(Bool()) val pop = Input(Bool()) val en = Input(Bool()) - val dataIn = Input(UInt(32)) - val dataOut = Output(UInt(32)) + val dataIn = Input(UInt.width(32)) + val dataOut = Output(UInt.width(32)) }) val stack_mem = Mem(depth, UInt(width = 32)) @@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module { val out = Reg(init = UInt(0, width = 32)) when (io.en) { - when(io.push && (sp < UInt(depth))) { + when(io.push && (sp < UInt.Lit(depth))) { stack_mem(sp) := io.dataIn - sp := sp +% UInt(1) - } .elsewhen(io.pop && (sp > UInt(0))) { - sp := sp -% UInt(1) + sp := sp +% UInt.Lit(1) + } .elsewhen(io.pop && (sp > UInt.Lit(0))) { + sp := sp -% UInt.Lit(1) } - when (sp > UInt(0)) { - out := stack_mem(sp -% UInt(1)) + when (sp > UInt.Lit(0)) { + out := stack_mem(sp -% UInt.Lit(1)) } } io.dataOut := out diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 6ebe0875..75c4278f 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -14,8 +14,8 @@ class Tbl(w: Int, n: Int) extends Module { val wi = Input(UInt(log2Up(n))) val ri = Input(UInt(log2Up(n))) val we = Input(Bool()) - val d = Input(UInt(w)) - val o = Output(UInt(w)) + val d = Input(UInt.width(w)) + val o = Output(UInt.width(w)) }) val m = Mem(n, UInt(width = w)) io.o := m(io.ri) @@ -32,13 +32,13 @@ class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends Basi val dut = Module(new Tbl(w, n)) val vvalues = Vec(values.map(UInt(_))) val vidxs = Vec(idxs.map(UInt(_))) - val prev_idx = vidxs(cnt - UInt(1)) - val prev_value = vvalues(cnt - UInt(1)) + val prev_idx = vidxs(cnt - UInt.Lit(1)) + val prev_value = vvalues(cnt - UInt.Lit(1)) dut.io.wi := vidxs(cnt) dut.io.ri := prev_idx dut.io.we := Bool(true) //TODO enSequence dut.io.d := vvalues(cnt) - when (cnt > UInt(0)) { + when (cnt > UInt.Lit(0)) { when (prev_idx === vidxs(cnt)) { assert(dut.io.o === vvalues(cnt)) } .otherwise { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index 2f3e9368..4c1e41c8 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -20,17 +20,17 @@ class FinishTester extends BasicTester { stop() } - val test_wire = Wire(UInt(1, width = test_wire_width)) + val test_wire = UInt(1, width = test_wire_width) // though we just set test_wire to 1, the assert below will pass because // the finish will change its value - assert(test_wire === UInt(test_wire_override_value)) + assert(test_wire === UInt.Lit(test_wire_override_value)) /** In finish we use last connect semantics to alter the test_wire in the circuit * with a new value */ override def finish(): Unit = { - test_wire := UInt(test_wire_override_value) + test_wire := UInt.Lit(test_wire_override_value) } } diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index ca83ee1d..812f822d 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -8,15 +8,15 @@ import chisel3.testers.BasicTester class UIntOps extends Module { val io = IO(new Bundle { - val a = Input(UInt(16)) - val b = Input(UInt(16)) - val addout = Output(UInt(16)) - val subout = Output(UInt(16)) - val timesout = Output(UInt(16)) - val divout = Output(UInt(16)) - val modout = Output(UInt(16)) - val lshiftout = Output(UInt(16)) - val rshiftout = Output(UInt(16)) + val a = Input(UInt.width(16)) + val b = Input(UInt.width(16)) + val addout = Output(UInt.width(16)) + val subout = Output(UInt.width(16)) + val timesout = Output(UInt.width(16)) + val divout = Output(UInt.width(16)) + val modout = Output(UInt.width(16)) + val lshiftout = Output(UInt.width(16)) + val rshiftout = Output(UInt.width(16)) val lessout = Output(Bool()) val greatout = Output(Bool()) val eqout = Output(Bool()) @@ -31,10 +31,10 @@ class UIntOps extends Module { io.addout := a +% b io.subout := a -% b io.timesout := (a * b)(15, 0) - io.divout := a / Mux(b === UInt(0), UInt(1), b) + io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b) // io.modout := a % b // TODO: - io.modout := UInt(0) + io.modout := UInt.Lit(0) io.lshiftout := (a << b(3, 0))(15, 0) io.rshiftout := a >> b io.lessout := a < b @@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) { class GoodBoolConversion extends Module { val io = IO(new Bundle { - val u = Input(UInt(1)) + val u = Input(UInt.width(1)) val b = Output(Bool()) }) io.b := io.u.toBool diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index b90c1f09..cdb1ba8d 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -12,7 +12,7 @@ import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? for ((a,b) <- v.zip(values)) { - assert(a === UInt(b)) + assert(a === UInt.Lit(b)) } stop() } @@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester { val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt - when (cnt >= UInt(n)) { - val expected = cnt - UInt(n) + when (cnt >= UInt.Lit(n)) { + val expected = cnt - UInt.Lit(n) assert(shifter(0) === expected) } when (wrap) { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 5f3d3e61..58aa43e7 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -13,19 +13,19 @@ class WhenTester() extends BasicTester { when(Bool(true)) { cnt.inc() } val out = Wire(UInt(width=3)) - when(cnt.value === UInt(0)) { - out := UInt(1) - } .elsewhen (cnt.value === UInt(1)) { - out := UInt(2) - } .elsewhen (cnt.value === UInt(2)) { - out := UInt(3) + when(cnt.value === UInt.Lit(0)) { + out := UInt.Lit(1) + } .elsewhen (cnt.value === UInt.Lit(1)) { + out := UInt.Lit(2) + } .elsewhen (cnt.value === UInt.Lit(2)) { + out := UInt.Lit(3) } .otherwise { - out := UInt(0) + out := UInt.Lit(0) } - assert(out === cnt.value + UInt(1)) + assert(out === cnt.value + UInt.Lit(1)) - when(cnt.value === UInt(3)) { + when(cnt.value === UInt.Lit(3)) { stop() } } @@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester { when(Bool(true)) { cnt.inc() } val out = Wire(UInt(width=3)) - when(cnt.value <= UInt(0)) { - out := UInt(1) - } .elsewhen (cnt.value <= UInt(1)) { - out := UInt(2) - } .elsewhen (cnt.value <= UInt(2)) { - out := UInt(3) + when(cnt.value <= UInt.Lit(0)) { + out := UInt.Lit(1) + } .elsewhen (cnt.value <= UInt.Lit(1)) { + out := UInt.Lit(2) + } .elsewhen (cnt.value <= UInt.Lit(2)) { + out := UInt.Lit(3) } .otherwise { - out := UInt(0) + out := UInt.Lit(0) } - assert(out === cnt.value + UInt(1)) + assert(out === cnt.value + UInt.Lit(1)) - when(cnt.value === UInt(3)) { + when(cnt.value === UInt.Lit(3)) { stop() } } |